Cientificos

74ABT573 Octal D-Type Latch with TRI-STATE Outputs

October 1995

74ABT573 Octal D-Type Latch with TRI-STATE Outputs
General Description
The ’ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs This device is functionally identical to the ’ABT373 but has different pinouts
Y Y Y Y

Y

Features
Y Y Y Y

Y Y

Inputs andoutputs on opposite sides of package allow easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’ABT373 TRI-STATE outputs for bus interfacing

Y

Output sink capability of 64 mA source capability of 32 mA Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50 pF and 250 pF loadsGuaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection High impedance glitch-free bus loading during entire power up and power down Nondestructive hot insertion capability

Commercial 74ABT573CSC (Note 1) 74ABT573CSJ (Note 1) 74ABT573CMSA (Note 1) 74ABT573CMTC (Notes 1 2)

Package Number M20B M20D MSA20 MTC20

Package Description 20-Lead (0300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Molded Shrink Small Outline EIAJ Type II 20-Lead Molded Thin Shrink Small Outline JEDEC

Note 1 Devices also available in 13 reel Use suffix e SCX SJX MSAX and MTCX Note 2 Contact factory for package availability

Connection Diagram
Pin Assignment for SOIC and SSOP Pin Names D0 –D7 LE OE O0 –O7Description Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs

TL F 11548 – 1

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

TL F 11548

RRD-B30M125 Printed in U S A

Functional Description
The ’ABT573 contains eight D-type latches with TRI-STATE output buffersWhen the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE)input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Function Table Inputs OE L L L H LE H H L X D H L X X Outputs O H L O0 Z

H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial O0 e Value stored from previous clock cycle

Logic Diagram

TL F 11548 – 3Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2

Absolute Maximum Ratings (Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabledor Power-Off State in the HIGH State Current Applied to Output in LOW State (Max)
b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA

DC Latchup Source Current Over Voltage Latchup (I O)

b 500 mA

10V

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functionaloperation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs

Recommended Operating Conditions
Free Air Ambient Temperature Commercial Supply Voltage Commercial Minimum Input Edge Rate Data Input Enable Input
b 40 C to a 85 C a 4 5V to a 5 5V

b 0 5V to a 5 5V b 0 5V to VCC

Twice the rated IOL (mA)

(DV Dt) 50 mV ns 20 mV ns...