Computacion

Código VHDL:

library ieee;
use ieee.std_logic_1164.all;
entity destado is port(
clk, reset, w: in std_logic;
z : out std_logic );

attribute pin_numbers of destado :entity is
"clk:1 reset:13 w:2 z:23";
end destado;

architecture funcion of destado is
type estados is (A, B, C, D);
signal edo_presente, edo_futuro : estados;

Begin
process(edo_presente, w)begin
case edo_presente is
when A=>
z <= '0';
if(w='0')then
edo_futuro<=A;
else
edo_futuro<=B;
end if;
when B=>
z <= '0';if(w='0')then
edo_futuro<=B;

else
edo_futuro<=C;
end if;
when C=>
z <= '0';
if(w='0')then
edo_futuro<=C;
else
edo_futuro<=D;end if;
when D=>
z <= '1';
if(w='0')then
edo_futuro<=D;
else
edo_futuro<=A;
end if;
end case;
end process;

Process(reset, clk)Begin
if(reset='0')then
edo_presente<=A;
elsif(clk'event and clk='1')then
edo_presente <= edo_futuro;
end if;
end process;

end funcion;

libraryieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mealy is
port(clk ,reset , w: in std_logic;
z: out std_logic );

attribute pin_numbers of mealy :entity is
"clk:1 reset:13 w:2 z:23";
end mealy;

architecture funcion of mealy is
type state_type is(A,B,C,D);
signal F :state_type;

begin
process(reset, clk)
begin
if(reset='1') then
F<=A;
elsif (clk'event and clk='1') then
case F is

when A=>

if (w='0') then
F <= A;
else
F<=B;
end if;

when B=>
if(w='0') then
F<=A;
else
F<=D;
end if;

when C=>
if (w='0') then
F<=A;
else
F<=C;

end if;

when D=>
if (w='0') then...