SRPS015 – D3972, FEBRUARY 1992
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Second-Generation PLD Architecture High-Performance Operation: fmax (External Feedback) . . . 71 MHz Propagation Delay . . . 10 ns Max Increased Logic Power – Up to 22 Inputs and 10 Outputs Increased Product Terms – Average of 12 Per Output Variable ProductTerm Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control Power-Up Clear on Registered Outputs TTL-Level Preload for Improved Testability Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability Fast Programming, High Programming Yield, and UnsurpassedReliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features Dependable Texas Instruments Quality and Reliability Package Options Include Plastic Dual-In-Line and Chip Carrier Packages
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The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functionalequivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Thesedevices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. Further advantages canbe seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.
This device is covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of TexasInstruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Copyright © 1992, Texas Instruments Incorporated
1TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-highclock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output...