Diseño termico en electronica (ingles) - electronics thermal modeling

A Short Tutorial on Thermal Modeling and Management
Kevin Skadron, Mircea Stan, co-PIs Wei Huang, Karthik Sankaranaryanan
© 2008, Kevin Skadron

Univ. of Virginia HotSpot group

Cooking-aware computing

© 2008, Kevin Skadron

Some chips rated for 100°C+

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Overview
1. 2. 3. 4. 5. 6.
© 2008, Kevin Skadron

What is thermal-aware design? Why thermal? Some basic heat transferconcepts Thermal management HotSpot thermal model Thermal sensor issues

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Metrics and Design Objectives
• Power • Energy
Design for power delivery

• Average power, instantaneous power, peak power
Low-Power Design Power-Aware/ • Energy (MIPS/W) = heat Energy-Efficient 2/W) • Energy-Delay product (MIPS Design • Energy-Delay2 product (MIPS3/W) – voltage indep.

• Temperature

(Zyuban,GVLSI’02)

© 2008, Kevin Skadron

• Correlated with power density over sufficiently large time periods Temperature-Aware Design • Localized T, short time scales vs. • Coarse granularities
Power-Aware Design
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Key Differences: Power vs. Thermal
• Energy efficiency
• Reclaim slack • Most benefit when system isn’t working hard • Best effort

•

Thermal
• Never exceed max temperature(eg, 100° C) – Best effort not sufficient • Most important when system is working hard – This means that throttling tends to affect performance severely • Must provision for worst-case expected workload
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© 2008, Kevin Skadron

Case Study: GPUs
• • For 3D games, frame rate is very important A board that slows down during the most challenging parts of the game will be unacceptable to gamersMust provision cooling for most difficult frame of most difficult frame This means that throttling is only a failsafe But we want to reduce cooling costs How?

• • • •

© 2008, Kevin Skadron

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Trends in Power Density
1000

Nuclear Reactor Nuclear Reactor

Rocket Nozzle

Watts/cm 2

100

Pentium® 4

Hot plate
10

Pentium® III Pentium® II

i386 i486
© 2008, KevinSkadron

Pentium® Pro Pentium®

1
1.5μ 1μ 0.7μ 0.5μ 0.35μ 0.25μ 0.18μ 0.13μ 0.1μ 0.07μ

* “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note - 1999.
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ITRS Projections
2001 – was 0.4
Year Tech node (nm) Vdd (high perf) (V) Vdd (low power) (V) Frequency (high perf) (GHz) High-perf w/ heatsinkCost-performance Hand-held 2003 100 1.2 1.0 3.0 149 80 2.1 2006 2010 70 45 1.1 1.0 0.9 0.7 6.7 15.1 Max power (W) 180 198 98 119 3.0 3.0 2013 32 0.9 0.6 23.0 198 137 3.0 2016 22 0.8 0.5 39.7 198 151 3.0

ITRS 2006 update

2001 – was 288

© 2008, Kevin Skadron

• Clock frequency targets don’t account for trend toward simpler cores in multicore • Growth in power density means cooling costscontinue to grow • High-performance designs seem to be shifting away from clock frequency toward # cores

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Leakage
• • • • Vdd reductions were stopped by leakage Lower Vdd => Vth must be lower Leakage is exponential in Vth Leakage is also exponential in T

© 2008, Kevin Skadron

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Moore’s Law and Dennard Scaling
• • Moore’s Law: transistor density doubles every N years (currently N ~2) Dennard Scaling (constant electric field)
• Shrink feature size by k (typ. 0.7), hold electric field constant • Area scales by k2 (1/2) , C, V, delay reduce by k • P ≅ CV2f ⇒ P goes down by k2
© 2008, Kevin Skadron

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Actual Power
Core 2 Duo
100
Pentium® II Pentium® Pro Pentium® 4 Pentium®

Max Power (Watts)

Pentium® III

10
Pentium® Pentium® w/MMX tech.

i486 i386

©2008, Kevin Skadron

1
1.5μ 1μ 0.8μ 0.6μ 0.35μ 0.25μ 0.18μ 0.13μ

Source: Intel

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The Real Power Wall
• • Vdd scaling is coming to a halt
• Currently 0.9-1.0V, scaling only ~2.5%/gen [ITRS’06]

Even if we generously assume C scales and frequency is flat
• P ≅ CV2f ⇒ 0.7 (0.9752) (1) = 0.66 P/A = 0.66/0.5 = 1.33 And this is very optimistic, because C probably scales more like 0.8...