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DM74LS181 4-Bit Arithmetic Logic Unit

October 1988 Revised April 2000

DM74LS181 4-Bit Arithmetic Logic Unit
General Description
The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations.

s Provides 16 arithmetic operations: add, subtract, compare, double, plus twelveother arithmetic operations s Provides all 16 logic operations of two variables: exclusive-OR, compare, AND, NAND, OR, NOR, plus ten other logic operations s Full lookahead for high speed arithmetic operation on long words

Ordering Code:
Order Number DM74LS181N Package Number N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Logic Symbols
ActiveHigh Operands

Connection Diagram

Active Low Operands

Pin Descriptions
Pin Names A0–A3 B0–B3 S0–S3 M Cn F0–F3
VCC = Pin 24 GND = Pin 12

Description Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry OutputA=B G P Cn+4

© 2000 Fairchild Semiconductor Corporation



Functional Description
The DM74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0–S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on activeHIGH or active LOW operands. The Function Table lists these operations When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carrylookahead and provides for either ripple carry between devices using the Cn+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the SUBTRACT mode, P indicates that F is zero or less, while G indicates that F is less than zero. P and G are notaffected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit. One carry lookahead package is required for each group of four DM74LS181 devices. Carry lookahead canbe provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wiredAND with other A = B outputs to give a comparison for more than four bits.The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actuallyperformed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are...
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