Guide to risc processors

Guide to RISC Processors

Sivarama P. Dandamudi

Guide to RISC Processors
for Programmers and Engineers

Sivarama P. Dandamudi School of Computer Science Carleton University Ottawa, ON K1S 5B6 Canada sivarama@scs.carleton.ca

Library of Congress Cataloging-in-Publication Data Dandamudi, Sivarama P., 1955– Guide to RISC processors / Sivarama P. Dandamudi. p. cm. Includesbibliographical references and index. ISBN 0-387-21017-2 (alk. paper) 1. Reduced instruction set computers. 2. Computer architecture. 3. Assembler language (Computer program language) 4. Microprocessors—Programming. I. Title. QA76.5.D2515 2004 004.3—dc22 2004051373 ISBN 0-387-21017-2 Printed on acid-free paper. © 2005 Springer Science+Business Media, Inc. All rights reserved. This work may not be translated orcopied in whole or in part without the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known orhereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed in the United States of America. 9 8 7 6 5 4 3 2 1 springeronline.com (HAM)

SPIN 10984949

To my parents, SubbaRao and Prameela Rani, my wife, Sobha, and my daughter, Veda

Preface

Popular processor designs can be broadly divided into two categories: Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). The dominant processor in the PC market, Pentium, belongs to the CISC category. However, the recent trend is to use the RISC designs. Even Intel has moved from CISC toRISC design for their 64-bit processor. The main objective of this book is to provide a guide to the architecture and assembly language of the popular RISC processors. In all, we cover five RISC designs in a comprehensive manner. To explore RISC assembly language, we selected the MIPS processor, which is pedagogically appealing as it closely adheres to the RISC principles. Furthermore, theavailability of the SPIM simulator allows us to use a PC to learn the MIPS assembly language.

Intended Use
This book is intended for computer professionals and university students. Anyone who is interested in learning about RISC processors will benefit from this book, which has been structured so that it can be used for self-study. The reader is assumed to have had some experience in a structured,high-level language such as C. However, the book does not assume extensive knowledge of any high-level language—only the basics are needed. Assembly language programming is part of several undergraduate curricula in computer science, computer engineering, and electrical engineering departments. This book can be used as a companion text in those courses that teach assembly language.

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Features
Here is a summary of the special features that set this book apart. • This probably is the only book on the market to cover five popular RISC architectures: MIPS, SPARC, PowerPC, Itanium, and ARM. • There is a methodical organization of chapters for a step-by-step introduction to the MIPS assembly language. • This book does not use fragments of code in examples. All examplesare complete in the sense that they can be assembled and run giving a better feeling as to how these programs work. • Source code for the MIPS assembly language program examples is available from the book’s Web site (www.scs.carleton.ca/˜sivarama/risc_book). • The book is self-contained and does not assume a background in computer organization. All necessary background material is presented in...