Implementación mips

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University of Ulster at Jordanstown
University of Applied Sciences, Augsburg

Master of Engineering
VLSI Design Project Report

Processor Implementation in VHDL
According to Computer Organisation & Design by David A. Patterson and John L. Hennessy Author(s): M. Linder M. Schmid

Supervisor(s): J. Färber A. Eder

Submitted: 06/07/07

Document Revision History, DesignersDepartment of Electrical Engineering

Document Revision History
Rev. 0.1 0.2 0.3 0.4 0.5 0.6 0.6.1 0.6.2 0.7 Date 15/05/2007 15/05/2007 29/05/2007 10/06/2007 30/06/2007 02/07/2007 02/07/2007 03/07/2007 04/07/2007 Author M. Schmid M. Linder M. Linder M. Linder M. Linder M. Linder M. Schmid M. Schmid M. Linder Description First draft release Features of the project Target Spec. (2.1, 2.2)Target Spec. (2.3) - include jump instruction to Target Spec. - Module Spec. of Control Module Spec. of Data Module Spec. of ALU and Memory Design Tasks - Module Spec. of Datapath - Synthesis Results - References 0.8 05/07/2007 M. Linder, M. Schmid - Synthesis Results - Source Code - Conclusion 1.0 05/07/2007 M. Linder, M. Schmid Final release

Designer(s)
M. Linder M. Schmidmichael-linder@web.de martin-werner.schmid@gmx.de

Contact
Michael Linder Angerstraße 8a 86356 Neusäß, Germany Phone: +49 (0) 176 22 93 58 30 Mail: michael-linder@web.de

Martin Schmid Fichtenstraße 2 86500 Kutzenhausen, Germany Phone: +49 (0) 160 92 94 91 54 Mail: martin-werner.schmid@gmx.de

M. Linder, M. Schmid

II

Contents
Department of Electrical Engineering

Contents
1Introduction................................................................................ 1
1.1 1.2 1.3 Starting from a Simple Implementation Scheme...................................1 Using Multicycle Implementations.........................................................2 Enhancing Performance with Pipelining................................................2

2

TargetSpecification................................................................... 3
2.1
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5

Building a Datapath............................................................................... 3
Major Components.................................................................................... 3 Components for Arithmetic and Logic Functions....................................... 4 Loadword (lw) and store word (sw) instructions........................................ 5 Branch on equal instruction....................................................................... 6 Jump Instruction........................................................................................ 6

2.2
2.2.1 2.2.2 2.2.3 2.2.4

Simple ImplementationScheme............................................................7
Creating a Single Datapath....................................................................... 7 ALU Control............................................................................................... 8 Main Control.............................................................................................. 9 Disadvantages of a Single-CycleImplementation................................... 10

2.3
2.3.1 2.3.2 2.3.3

Multicycle Implementation...................................................................11
Additions and Changes in the Scheme.................................................... 11 Execution of Instructions in Clock Cycles................................................ 14 Defining the Control by a Finite StateMachine........................................ 18

3 4

Design Tasks............................................................................ 21 Module Specification............................................................... 22
4.1
4.1.1 4.1.2 4.1.3 4.1.4

ALU......................................................................................................22
Functional...
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