Ing Civil Informatico

Lab 3: Decomposing State machines: Traffic Light Controller
CEG 360/560 - EE 451/651

PURPOSE
Just like large procedures or subroutines in a programming language, large state machines are difficult to conceptualize, design, and debug. Therefore, when faced with a large state-machine problem, digital designers often look for opportunities to solve it with a collection of smaller statemachines. The purpose of this lab is to design and build a clocked synchronous state machine of moderate complexity. This design can be approached using the basic techniques discussed in Mano, Ch. 4, but such an approach would be a significant effort. In this lab, students will simplify the design process by decomposing the overall design into two sub-designs: a data unit and a control unit. This isa two-week lab.




ASSIGNMENT

Consider the intersection of a busy highway and a little used farmroad, shown below. There is a sensor on both sides of the farmroad that detects the presence of a car waiting to cross the highway. Our goal is to design a traffic light control for this intersection to grant right of way to the roads as defined below.
[pic]
Figure 1: (a) Highway/Farmroadintersection – Placement of lights and sensors.

The traffic light control is a state machine with two synchronous input signals (CARDETECT and RESET) and six synchronous output signals (HLG, HLY, HLR, FLG, FLY, FLR) that control the traffic signal lights. The state machine to be designed must realize the following operational characteristics described below:
• The assertion of the CARDETECTinput signal (denoted C in Figure 1) indicates the detection of a vehicle on the farm road. As long as CARDETECT is not asserted, the highway has right of way. When CARDETECT is asserted, the farmroad is granted right of way (subject to limitations below).
• The farmroad may not retain right of way for longer than trightofway (even if CARDETECT is asserted).
• Once relinquished, the farmroadmay not be granted right of way again for at least trightofway.
• Before a road can gain right of way, the road which currently has right of way (indicated with a Green traffic signal) must relinquish right of way (indicated by changing to a Yellow traffic signal for some period of time tyellow and then changing to a Red signal). One road should always have right of way.
• Right of way shouldnever be granted to both roads at once – even if your circuit somehow gets into an unexpected state. We must guarantee that the controller is risk-free – lives are on the line.
• If you have any questions about the proper operation of this device, ask your TA. If you must make any assumptions, note them in your lab notebook.


PRELAB (WEEK ONE): Data unit design using Shift Registers(10 pts.) The goal of the first week is to design the data unit for the project.

Data units are used for storing, combining and processing data. Usually, a data unit consists of multi-bit counters, shift-registers, and ALUs which increment, shift, or modify register contents according to the control signals applied to the unit. The inputs to the data unit consist of primary inputs (usually)and commands from the control unit (control signals). The outputs of the data unit consist of the primary outputs (usually) and status signals that provide feedback to the control unit.

You will need to consider how to best decompose this design - it may take several attempts to get something that works well. You may use whichever control and status signals you wish (subject to therestrictions below). The number and type of control and status signals is up to you; well though-out selections will reduce the required design effort. Consider carefully the actions that the control unit will need to request.

In designing the data unit for this project, you are subject to the following restrictions:
• The data unit must contain two 4-bit shift-registers and one 4-bit counter. This...