Irf2110

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Data Sheet No. PD60147 Rev.T

IR2110(S)/IR2113(S) & (PbF)
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation • • • • • • • •
Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20VLogic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE

Product Summary
VOFFSET (IR2110) (IR2113) IO+/VOUT ton/off (typ.) 500V max. 600V max. 2A / 2A 10 - 20V 120 & 94 ns

Delay Matching (IR2110) 10 ns max. (IR2113) 20ns max.Packages

Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output 16-Lead SOIC 14-Lead PDIP channels. Proprietary HVIC and latch immune CMOS technologies IR2110S/IR2113S IR2110/IR2113 enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic.The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.

Typical Connection
HO VDD HIN SD LIN V SS VCC VDD HIN SD LINVSS VCC COM LO VB VS

up to 500V or 600V

TO LOAD

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

www.irf.com

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IR2110(S)/IR2113(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond whichdamage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol
VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA TJ TS TL

Definition
High side floating supply voltage (IR2110) (IR2113)High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN & SD) Allowable offset supply voltage transient (figure 2) Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Leadtemperature (soldering, 10 seconds) (14 lead DIP) (16 lead SOIC) (14 lead DIP) (16 lead SOIC)

Min.
-0.3 -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 — — — — — — -55 —

Max.
525 625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 150 150 300

Units

V

V/ns W

°C/W

°C

Recommended Operating Conditions
The input/output logic timing diagram isshown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 36 and 37.

Symbol
VB VS VHO VCC VLO VDD VSS VIN TA

Definition
High side floating supply absolute voltage High side floating supply offset voltageHigh side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN & SD) Ambient temperature (IR2110) (IR2113)

Min.
VS + 10 Note 1 Note 1 VS 10 0 VSS + 3 -5 (Note 2) VSS -40

Max.
VS + 20 500 600 VB 20 VCC VSS + 20 5 VDD 125

Units

V

°C

Note 1: Logic operational for VS of -4 to...
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