Lista intel microprocedador

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ntroduced November 1, 1995
Precursor to Pentium II and III
Primarily used in server systems
Socket 8 processor package (387 pins) (Dual SPGA)
Number of transistors 5.5 million
Family 6 model 1
0.6 µm process technology
16 KB L1 cache
256 KB integrated L2 cache
60 MHz system bus clock rate
Variants
150 MHz
0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
Number oftransistors 5.5 million
512 KB or 256 KB integrated L2 cache
60 or 66 MHz system bus clock rate
Variants
166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 512 KB 0.35 µmcache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997

Pentium II
Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bit performance
242-pin Slot 1 (SEC) processor package
Slot 1
Number of transistors 7.5 million
32 KB L1 cache
512 KB ½ bandwidth external L2 cache
The only Pentium II that did not have the L2 cache at ½bandwidth of the core was the Pentium II 450 PE.
Klamath – 0.35 µm process technology (233, 266, 300 MHz)
66 MHz system bus clock rate
Family 6 model 3
Variants
233, 266, 300 MHz Introduced May 7, 1997
Deschutes – 0.25 µm process technology (333, 350, 400, 450 MHz)
Introduced January 26, 1998
66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models afterFamily 6 model 5
Variants
333 MHz Introduced January 26, 1998
350, 400 MHz Introduced April 15, 1998
450 MHz Introduced August 24, 1998
233, 266 MHz (Mobile) Introduced April 2, 1998
333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo
300 MHz (Mobile) Introduced September 9, 1998
333 MHz (Mobile)

Celeron (Pentium II-based)
Covington– 0.25 µm process technology
Introduced April 15, 1998
242-pin Slot 1 SEPP (Single Edge Processor Package)
Number of transistors 7.5 million
66 MHz system bus clock rate
Slot 1
32 KB L1 cache
No L2 cache
Variants
266 MHz Introduced April 15, 1998
300 MHz Introduced June 9, 1998
Mendocino – 0.25 µm process technology
Introduced August 24, 1998
242-pin Slot 1 SEPP (Single EdgeProcessor Package), Socket 370 PPGA package
Number of transistors 19 million
66 MHz system bus clock rate
Slot 1, Socket 370
32 KB L1 cache
128 KB integrated cache
Family 6 model 6
Variants
300, 333 MHz Introduced August 24, 1998
366, 400 MHz Introduced January 4, 1999
433 MHz Introduced March 22, 1999
466 MHz
500 MHz Introduced August 2, 1999
533 MHz Introduced January 4, 2000
266 MHz(Mobile)
300 MHz (Mobile)
333 MHz (Mobile) Introduced April 5, 1999
366 MHz (Mobile)
400 MHz (Mobile)
433 MHz (Mobile)
450 MHz (Mobile) Introduced February 14, 2000
466 MHz (Mobile)
500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)
Introduced June 29, 1998
See main entry

Pentium III
Katmai – 0.25 µm process technology
Introduced February 26, 1999Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
Number of transistors 9.5 million
512 KB ½ bandwidth L2 External cache
242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
System Bus clock rate 100 MHz, 133 MHz (B-models)
Slot 1
Family 6 model 7
Variants
450, 500 MHz Introduced February 26, 1999
550 MHz Introduced May 17, 1999
600 MHzIntroduced August 2, 1999
533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
Coppermine – 0.18 µm process technology
Introduced October 25, 1999
Number of transistors 28.1 million
256 KB Advanced Transfer L2 Cache (Integrated)
242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
System Bus clock rate 100...
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