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CPU12
Reference Manual

M68HC12 & HCS12
Microcontrollers
CPU12RM/AD Rev. 5 6/2003

MOTOROLA.COM/SEMICONDUCTORS

CPU12
Reference Manual
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. This product incorporates SuperFlash® technology licensed from SST. CPU12 — Rev.5.0 MOTOROLA

© Motorola, Inc., 2003 Reference Manual 3

Revision History
Revision History
Date April, 2002 May, 2003 Revision Level 3.0 4.0 Description Incorporated information covering HCS12 Family of 16-bit MCUs throughout the book. Limited release with additional HCS12 Family information incorporated throughout the book. 6.7 Glossary — Corrected table entries for the followinginstructions: ADDD, ANDA, ANDB, BCLR, CPD, DBEQ, DEC, EMAXM, EMIND, LSL, and NEG Table A-1. Instruction Set Summary — Corrected M68HC12 access detail entry for ADCA [D,xysp] Page Number(s) Throughout Throughout

June, 2003

5.0

111, 112, 113, 123, 161, 166, 168, 178, 179, 227, and 243 387

Reference Manual 4 Revision History

CPU12 — Rev. 5.0 MOTOROLA

Reference Manual — CPU12

List ofSections

Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Section 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Addressing Modes . . . . . . . . . . . . . . . . . . . . . 33 Section 4. Instruction Queue . . . . . . . . . . . . . . . . . . . . . . 51 Section 5. Instruction Set Overview . . . . . . . . . . . . . . . . 59 Section 6.Instruction Glossary . . . . . . . . . . . . . . . . . . . . 91 Section 7. Exception Processing. . . . . . . . . . . . . . . . . . 315 Section 8. Instruction Queue . . . . . . . . . . . . . . . . . . . . 327 Section 9. Fuzzy Logic Support . . . . . . . . . . . . . . . . . . . 341 Appendix A. Instruction Reference . . . . . . . . . . . . . . . . 381 Appendix B. M68HC11 to CPU12 Upgrade Path. . . .. . 409 Appendix C. High-Level Language Support . . . . . . . . . 431 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

CPU12 — Rev. 5.0 MOTOROLA List of Sections

Reference Manual 5

List of Sections

Reference Manual 6 List of Sections

CPU12 — Rev. 5.0 MOTOROLA

Reference Manual — CPU12

Table of Contents

Section 1. Introduction
1.11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3 Symbols and Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.1 Abbreviations for System Resources . . . . . . . . . . . . . . . . . . 20 1.3.2 Memory and Addressing .. . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.3 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.4 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Section 2. Overview
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 Programming Model . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.1 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.2 Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.4 Program Counter . . . . . . . . . . . . . . ....
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