Practica 2

Laboratory Exercise 2
Numbers and Displays
This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition. Part I We wish to display on the 7-segment displays HEX3 to HEX0 the values set by the switches SW15−0 . Let the values denoted by SW15−12 , SW11−8 , SW7−4 and SW3−0 be displayed on HEX3, HEX2, HEX1 andHEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares. 1. Create a new project which will be used to implement the desired circuit on the Altera DE2-series board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. You should use only simple Verilog assignstatements in your code and specify each logic function as a Boolean expression. 2. Write a Verilog file that provides the necessary functionality. Include this file in your project and assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual for the DE2-series board. The procedure for making pin assignments is described in the tutorial Quartus IIIntroduction using Verilog Design, which is available on the DE2-Series System CD and in the University Program section of Altera’s web site. 3. Compile the project and download the compiled circuit into the FPGA chip. 4. Test the functionality of your design by toggling the switches and observing the displays. Part II You are to design a circuit that converts a four-bit binary number V = v3 v2 v1v0 into its two-digit decimal equivalent D = d1 d0 . Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a Verilog module which includesthe comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). Your Verilog module should have the four-bit input V , the four-bit output M and the output z. The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else, case,or similar statements. Binary value 0000 0001 0010 ... 1001 1010 1011 1100 1101 1110 1111 Decimal digits 0 0 0 ... 0 1 1 1 1 1 1 0 1 2 ... 9 0 1 2 3 4 5

Table 1. Binary-to-decimal conversion values. 1

Perform the following steps: 1. Make a Quartus II project for your Verilog module. 2. Compile the circuit and use functional simulation to verify the correct operation of your comparator,multiplexers, and circuit A. 3. Augment your Verilog code to include circuit B in Figure 1 as well as the 7-segment decoder. Change the inputs and outputs of your code to use switches SW3−0 on the DE2-series board to represent the binary number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0 . Make sure to include in your project the required pin assignments for theDE2-series board. 4. Recompile the project, and then download the circuit into the FPGA chip. 5. Test your circuit by trying all possible values of V and observing the output displays.

d1 z Comparator Circuit B v3 0
0 1 7

0 5 4 3 d0 6 1 2

m3

v2

0 1

m2 7-segment decoder
7

0 5 4 3 6 1 2

v1

0 1

m1

v0

0 1

m0

Circuit A

Figure 1: Partial design of thebinary-to-decimal conversion circuit.

Part III Figure 2a shows a circuit for a full adder, which has the inputs a, b, and ci , and produces the outputs s and co . Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum co s = a + b + ci . Figure 2d shows how four instances of this full adder module can be used to design a circuit...