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ALU
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity alu is
port(
A,B: in std_logic_vector(2 downto 0);
M: instd_logic;
sel: in std_logic_vector(1 downto 0);
y:out std_logic_vector(3 downto 0));

end;
architecture behavioral of alu is
begin

process(M,A,B,sel)
begin

if M='0' then

case sel iswhen "00"=>y<= (('0'&A) and ('0'&B));
when "01"=>y<= (('0'&A) or ('0'&B));
when "10"=>y<= (('0'&A) xor ('0'&B));
when "11"=>y<= not(('0'&A));
endcase;

elsif M='1' then
y<=('0'&A)+('0'&B);

end if;
end process;
end behavioral;

BCD A SIETE SEGMENTOS

library ieee;
use ieee.std_logic_1164.all;

entity display isport(
BCD: in std_logic_vector ( 3 downto 0 );
SEGMENTOS: out std_logic_vector ( 6 downto 0 ) );

end;

architecture behavioral of display is
begin
process(BCD)
begin
case BCD is--abcdefg
when "0000" => SEGMENTOS <= "1111110"; -- 0
when "0001" => SEGMENTOS <= "0110000"; -- 1
when "0010" => SEGMENTOS <= "1101101"; -- 2when "0011" => SEGMENTOS <= "1111001"; -- 3
when "0100" => SEGMENTOS <= "0110011"; -- 4
when "0101" => SEGMENTOS <= "1011011"; -- 5
when "0110"=> SEGMENTOS <= "1011111"; -- 6
when "0111" => SEGMENTOS <= "1110000"; -- 7
when "1000" => SEGMENTOS <= "1111111"; -- 8
when "1001" => SEGMENTOS <="1111011"; -- 9
when others => SEGMENTOS <= "0000000"; -- APAGADO
end case;
end process;
end behavioral;

CODIFICADOR

library ieee;
use ieee.std_logic_1164.all;
entityCod is
port ( Entrada: in std_logic_vector(7 downto 0);
Salida: out std_logic_vector(2 downto 0));
end;
architecture funcion of Cod is
begin
process(Entrada)
begin
case Entrada...
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