The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 11-1.
Stop Mode EPPAR[2n, 2n + 1]
Edge Detect Logic
EPFR[n]D0 Q D1 D0 Q D1 To Interrupt Controller
EPPDR[n] Synchronizer EPIER[n] Rising Edge of System Clock
Figure 11-1. EPORT Block Diagram
Low-Power Mode Operation
This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 7, “Power Management.” Table 11-1 shows EPORTmodule operation in low-power modes, and describes how this module may exit from each mode. NOTE The low-power interrupt control register (LPICR) in the System Control Module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode.
MCF5282 Coldfire Microcontroller User’s Manual, Rev. 2.3 Freescale Semiconductor 11-1
Edge Port Module (EPORT)Table 11-1. Edge Port Module Operation in Low-power Modes
Low-power Mode Wait Doze Stop EPORT Operation Normal Normal Level-sensing Only Mode Exit Any IRQx Interrupt at or above level in LPICR Any IRQx Interrupt at or above level in LPICR Any IRQx Interrupt set for level-sensing at or above level in LPICR
In wait and doze modes, the EPORT module continues to operate as it does in run mode. Itmay be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. NOTE Theinput pin synchronizer is bypassed for the level-detect logic since no clocks are available.
Interrupt/General-Purpose I/O Pin Descriptions
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the risingedge of CLKOUT. These pins use Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are highat reset.
MCF5282 Coldfire Microcontroller User’s Manual, Rev. 2.3 11-2 Freescale Semiconductor
Memory Map and Registers
Memory Map and Registers
This subsection describes the memory map and register structure.
Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of 0x0013_0000.
Table 11-2.Edge Port Module Memory Map
IPSBAR Offset 0x0013_0000 Bits 15–8 Bits 7–0 Access1 S S S/U S/U
EPORT Pin Assignment Register (EPPAR)
0x0013_0002 EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER) 0x0013_0004 0x0013_0006
EPORT Data Register (EPDR) EPORT Flag Register (EPFR)
EPORT Pin Data Register (EPPDR) Reserved
S = CPU supervisor mode access only.S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 Writing to reserved address locations has no effect, and reading returns 0s.
The EPORT programming model consists of these registers: • The EPORT pin assignment register (EPPAR) controls the function of each pin...