Reference manual demoqe128

M

MC9S08QE128 MC9S08QE96 MC9S08QE64
Reference Manual
HCS08 Microcontrollers
Related Documentation:
• MC9S08QE128 (Data Sheet) Contains pin assignments and diagrams, all electrical specifications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com

MC9S08QE128RM Rev. 2 6/2007

freescale.com

MC9S08QE128 Series Features
8-BitHCS08 Central Processor Unit (CPU)
• Up to 50.33-MHz HCS08 CPU from 3.6 V to 2.1 V, and 20-MHz CPU at 2.1 V to 1.8 V across temperature range of –40˚C to 85˚C • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources

Development Support
• Single-wire background debug interface • Breakpoint capability to allow single breakpoint setting during in-circuitdebugging (plus two more breakpoints in on-chip debug module) • On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints.

On-Chip Memory
• Flash read/program/erase over full operating voltage and temperature • Random-accessmemory (RAM) • Security circuitry to prevent unauthorized access to RAM and flash contents

Peripherals
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V • ACMPx — Two analog comparators with selectable interrupt on rising, falling, oreither edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 • SCIx — Two full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge • SPIx— Two serial peripheral interfaces with full-duplex or single-wire bidirectional;double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting • IICx — Two IICs with; up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing • TPMx — One 6-channel (TPM3) and two 3-channel (TPM1 and TPM2); Selectable input capture, output compare,or buffered edge- or center-aligned PWM on each channel • RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes

Power-Saving Modes
• Two verylow power stop modes, one of which allows limited use of peripherals • Reduced power wait mode • Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • Very low power external oscillator that can be used in stop3 mode to provide accurate clock source to active peripherals • Very lowpower real time counter for use in run, wait, and stop modes with internal and external clock sources • 6 μs typical wake up time from stop3 mode

Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz • Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop(FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 2 MHz to 50.33 MHz

System Protection
• Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock • Low-voltage detection with reset or...