sdf dfgd dfg

ANALYSIS OF CASE STATEMENTS

The common practice is to use casez statement in RTL coding. Use of casex is strongly
discouraged. Now we will discuss whether casex is such a bad construct. Before we start
let me say, all case statements are synthesizable.
If someone is required to tell the differences between case, casez, casex constructs in
verilog, the answer will be the pretty familiarone:
casez treats 'z' as dont care.
casex treats 'z' & 'x' as dont care.
case treats 'z' & 'x' as it is.
Now lets go further and unearth the differences between them.
A common misconception is '?' does mean a don’t care, but it does not. It is just an
another representation of high impedence 'z'.
Ex:
case (sel)
00: mux_out = mux_in[0];
01: mux_out = mux_in[1];
1?: mux_out = mux_in[2];default: mux_out = mux_in[3];
endcase
In the above case statement if the intention is to match case item 3 to either 10 or 11 then
the code is absolutely wrong, because '?' doesnot mean a dont care. The actual case item
written is 1z.

Case statement:
Case statement treats x & z as it is. So a case expression containing x or z will only match
a case item containing x or z at thecorresponding bit positions. If no case item matches
then default item is executed. Its more like pattern matching. Any pattern formed from
the symbol set {0,1,x,z} will match its clone only.
Ex:
case (sel)
00: y = a;
01: y = b;
x0: y = c;
1x: y = d;
z0: y = e;
1?: y = f;
default: y = g;
endcase

Result:
sel
y
case item
00
a
00
11
g
default
xx
g
default
x0
c
x0
1z
f
1?
z1
gdefault
Note that when sel is 11, y is not assigned f, but is assigned the default value g.

Casez statement:
Casez statement treats z as dont care. It mean what it sounds, 'don’t care' (dont care
whether the bit is 0,1 or even x i.e, match z(?) to 0 or 1 or x or z).
Ex:
casez (sel)
00: y = a;
01: y = b;
x0: y = c;
1x: y = d;
z0: y = e;
1?: y = f;
default: y = g;
endcase
Result:sel
00
11
xx
x0

y
a
f
g
c

1z

d

z1

b

case item
00
1?
default
x0 (would have matched with z0(item 5) if item 3
is not present.)
1x (would have matched with z0(item 5) &
1?(item 6) also.)
01 (would have matched with 1?(item 6) also.)

The fact that x matches with z in casez gives the illusion 'x is being treated as a dont care
in casez'. What is exactly happeningis z, the dont care, is being matched to x. This will
be more clear if you admire the fact 'x will not be matched to 1 or 0 in casez'(but will
match z) .
The point we dicussed at the beginning that ? is not dont care is worth an explanation
here. ? is dont care only when used in casez, elsewhere it is nothing but z.

Casex statement:
Casex statement treats x and z as dont cares. x will bematched to 0 or 1 or z or x and z
will be matched to 0 or 1 or x or z.
Ex:
casex (sel)
00: y = a;
01: y = b;
x0: y = c;
1x: y = d;
z0: y = e;
1?: y = f;
default: y = g;
endcase
Result:
sel
00
11
xx
x0
1z

y
a
d
a
a
c

z1

b

case item
00
1x (would have matched with 1? also)
00 (would have matched with 1? also)
00 (would have matched with all items except 01)
x0(would have matched with all items except
00,01)
01 (would have matched with 1x, 1? also)

The summary of the discussion so far can be put up as follows:
Statement
Case

Expression contains
Binary
Binary
Binary
x
x
x
z (?)
z (?)
z (?)

Item contains
Binary
x
? (z)
Binary
x
? (z)
Binary
x
? (z)

Result
Match
Don’t match
Don’t match
Don’t match
Match
Don’t matchDon’t match
Don’t match
Match

Casez

Binary
Binary
Binary
x
x

Binary
x
? (z)
Binary
x

Match
Don’t match
Match
Don’t match
Match

x
z (?)

Match
Match

z (?)

x

Match

z (?)

? (z)

Match

Binary
Binary
Binary
x
x
x
z (?)

Binary
x
? (z)
Binary
x
? (z)
Binary

Match
Match
Match
Match
Match
Match
Match

z (?)

x

Match

z...