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CMOS Static RAM 16K (2K x 8-Bit)

IDT6116SA IDT6116LA

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Features
High-speed access and chip select times – Military: 20/25/35/45/55/70/90/120/150ns (max.) – Industrial: 20/25/35/45ns (max.) – Commercial: 15/20/25/35/45ns (max.) Low-power consumption Battery backup operation – 2V data retention voltage (LA version only) Produced with advanced CMOS high-performance technology CMOS processvirtually eliminates alpha particle soft-error rates Input and output directly TTL-compatible Static operation: no clocks or refresh required Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip, 24-pin SOIC and 24-pin SOJ Military product compliant to MIL-STD-833, Class B

Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized as 2K x 8. It is fabricated usingIDT's high-performance, high-reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby power mode, as long as CS remains HIGH. This capability provides significant system level power and cooling savings. The low-power (LA) version also offers a batterybackup data retention capability where the circuit typically consumes only 1µW to 4µW operating off a 2V battery. All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or ceramic DIP, 24-lead gull-wing SOIC, and 24-lead J-bend SOJproviding high board-level packing densities. Military grade product is manufactured in compliance to the latest version of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

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Functional Block Diagram
A0 V CC ADDRESS DECODER A 10 128 X 128 MEMORY ARRAY GND

I/O 0 INPUTDATA CIRCUIT I/O 7

I/O CONTROL

,
CS OE WE CONTROL CIRCUIT
3089 drw 01

FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC-3089/03

IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit)

Military, Commercial, and In dustrial Temperature Ranges

Pin Configurations
A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9WE OE A10 CS I/O 7 I/O 6 I/O 5 I/O 4 I/O3
3089 drw 02

Capacitance (TA = +25°C, f = 1.0 MHZ)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF
3089 tbl 03

P24-2 P24-1 D24-2 D24-1 SO24-2 SO24-4

NOTE: 1. This parameter is determined by device characterization, but is not production tested.

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Absolute Maximum Ratings(1)Symbol VTERM
(2)

DIP/SOIC/SOJ Top View Pin Description
Name A0 - A10 I/O0 - I/O7 CS WE OE VCC GND Description Address Inputs Data Input/Output Chip Select Write Enable Output Enable Power Ground
3089 tbl 01

Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current

Com'l. -0.5 to +7.0

Mil. -0.5 to+7.0

Unit V

TA TBIAS TSTG PT IOUT

0 to +70 -55 to +125 -55 to +125 1.0 50

-55 to +125 -65 to +135 -65 to +150 1.0 50

o

C C C

o

o

W mA
3089 tbl 04

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC +0.5V.

Truth Table(1)
Mode Standby Read Read Write CS H L L L OE X L H X WE X H H L I/O High-Z DATA OUT High-Z DATA IN
3089 tbl 02

NOTE: 1. H = VIH, L = VIL, X = Don't Care.

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