Unidad De Memoria

Unidad de memoria.
Código VHDL
----------------------------------------------------------------------------------
-- Company: ITO
-- Engineer: Edwako
-- Create Date: 11:24:56 03/01/2012
--Design Name: unidad de memoria
-- Module Name: Unidaddememoria - Behavioral
-- Project Name: Unidad de memoria
-- Additional Comments:
-- Unidad de memoria de 4 bits----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Unidaddememoria is
Port ( CLK : in STD_LOGIC;
Reset : inSTD_LOGIC;
Bin : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC;
En : in STD_LOGIC;
Out_Rom : out STD_LOGIC_VECTOR (3 downto 0));
end Unidaddememoria;-----------------------------------------------------------------------------------
architecture structural of Unidaddememoria is-----------------------------------------------------------------------------------
component Reg4 is -- MAR memory adress regristrer
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (3 downto 0);
En : inSTD_LOGIC);
end component;
------------------------------------------------------------------------------------
component ROM is --unidad de almacenamineto
Port ( Dir : in STD_LOGIC_VECTOR(3 downto 0);
CLK : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (3 downto 0) );
end component;------------------------------------------------------------------------------------
component Mux2a1 is -- selector entre señales nuevas y señales del Cont16
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);Salida : out STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC);
end component;
------------------------------------------------------------------------------------
component...