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VHDL Simulation Coding and Modeling Style Guide
Version 7.1.1 February 2004

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Copyright Notice and Proprietary Information

Copyright  2004 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The softwareand documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by thelicense agreement.

Right to Copy Documentation
The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page:“This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.”

Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to UnitedStates law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.

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SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

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BCView, Behavioral Compiler, BOA, BRT, Cedar, ClockTree Compiler, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Compiler, DesignSphere, DesignTime, Direct RTL, Direct Silicon Access, DW8051, DWPCI, ECL Compiler, ECO Compiler, ExpressModel, Floorplan Manager, FoundryModel, FPGA Compiler II, FPGAExpress, Frame Compiler, HDL Advisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Liberty, Library Compiler, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim, OpenVera, Physical Compiler, PowerCODE, PowerGate, Power Compiler, ProFPGA, Protocol Compiler, RoadRunner, Route Compiler, RTL Analyzer, Schematic Compiler, Scirocco, Shadow Debugger, SmartLicense, SmartModel Library,SourceLevel Design, SWIFT, Synopsys Eaglei, Synopsys EagleV, SystemC, System C (logo), Test Compiler, TestGen, TimeTracker, Timing Annotator, Trace-On-Demand, VCS, VCS Express, VCSi, VHDL Compiler, VHDL System Simulator, VirSim, VMC, and VSS are trademarks of Synopsys, Inc.

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DesignSphere and TAP-in are a service marks of Synopsys, Inc. All other product or company names may betrademarks of their respective owners.

Printed in the U.S.A. Document Order Number: 36547-000SA VHDL Simulation Coding and Modeling Style Guide, 7.1.1 Beta

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Contents
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SolvNet Online Help . . . . . . ....
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