74112
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Publicado: 14 de febrero de 2013
M54HC112 M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. . . . . . . .
HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) =2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R
DESCRIPTION The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTLcombined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truthtable. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
NC = No Internal Connection
October 1992
1/11
M54/M74HC112
TRUTH TABLE
INPUTS CLR L H L H H H H H
X: Don’t Care
OUTPUTS KX X X L L H H X CK X X X Q L H H Qn H L Qn Qn Q H L H Qn L H Qn Qn
PR H L L H H H H H
J X X X L H L H X
FUNCTION CLEAR PRESET NO CHANGE
TOGGLE NO CHANGE
PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 SYMBOL 1CK, 2CK 1K, 2K 1J, 2J 1PR, 2PR 1Q, 2Q 1Q, 2Q 1CLR, 2CLR GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 and2 Data Inputs: Flip-Flop 1 and 2 Set Inputs True Flip-Flop Outputs Complement Flip-Flop Outputs Reset inputs Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOL
LOGIC DIAGRAM (1/2 Package)
2/11
M54/M74HC112
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DCOutput Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under thesecondition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns
o
VCC = 2 V VCC= 4.5 V VCC = 6 V
3/11
M54/M74HC112
DC SPECIFICATIONS
Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-4.0 mA IO=-5.2 mA VI = IO= 20 µA VIH or V IL IO= 4.0 mA IO= 5.2 mA VI = VCC orGND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 2 TA = 25 C 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 20
o
Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 40 µA µA V V 1.5 3.15 4.2...
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. . . . . . . .
HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) =2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R
DESCRIPTION The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTLcombined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truthtable. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
NC = No Internal Connection
October 1992
1/11
M54/M74HC112
TRUTH TABLE
INPUTS CLR L H L H H H H H
X: Don’t Care
OUTPUTS KX X X L L H H X CK X X X Q L H H Qn H L Qn Qn Q H L H Qn L H Qn Qn
PR H L L H H H H H
J X X X L H L H X
FUNCTION CLEAR PRESET NO CHANGE
TOGGLE NO CHANGE
PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 SYMBOL 1CK, 2CK 1K, 2K 1J, 2J 1PR, 2PR 1Q, 2Q 1Q, 2Q 1CLR, 2CLR GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 and2 Data Inputs: Flip-Flop 1 and 2 Set Inputs True Flip-Flop Outputs Complement Flip-Flop Outputs Reset inputs Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOL
LOGIC DIAGRAM (1/2 Package)
2/11
M54/M74HC112
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DCOutput Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under thesecondition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns
o
VCC = 2 V VCC= 4.5 V VCC = 6 V
3/11
M54/M74HC112
DC SPECIFICATIONS
Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-4.0 mA IO=-5.2 mA VI = IO= 20 µA VIH or V IL IO= 4.0 mA IO= 5.2 mA VI = VCC orGND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 2 TA = 25 C 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 20
o
Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 40 µA µA V V 1.5 3.15 4.2...
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