7490

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Eachsection can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

SN54/74LS90 SN54/74LS92 SN54/74LS93

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
LOW POWER SCHOTTKY

• Low Power Consumption . . .Typically 45 mW • High Count Rates . . . Typically 42 MHz • Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary • Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a) HIGH CP0 CP1 CP1 MR1, MR2 MS1, MS2 Q0 Q1, Q2, Q3 Clock (Active LOW going edge) Input to ÷2 Section Clock (Active LOW going edge) Input to ÷5 Section (LS90), ÷6 Section (LS92) Clock(Active LOW going edge) Input to ÷8 Section (LS93) Master Reset (Clear) Inputs Master Set (Preset-9, LS90) Inputs Output from ÷2 Section (Notes b & c) Outputs from ÷5 (LS90), ÷6 (LS92), ÷8 (LS93) Sections (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 1.5 U.L.
14 14 1

J SUFFIX CERAMIC CASE 632-08

N SUFFIX PLASTIC CASE 646-06
1

2.0 U.L. 1.0 U.L. 0.25 U.L. 0.25U.L. 5 (2.5) U.L. 5 (2.5) U.L.

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) b. Temperature Ranges. c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 inputof the device. d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

LOGIC SYMBOL LS90
6 7 1 2 MS CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 6 7 12 11 9 8 VCC = PIN 5 GND = PIN 10 NC = PINS 2, 3, 4, 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC= PIN 4, 6, 7, 13

LS92

LS93

14 1

FAST AND LS TTL DATA 5-90

SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM LS90
MS1 MS2
6 7

CONNECTION DIAGRAM DIP (TOP VIEW)
CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2

14

S J DQ CP KC Q D

S J DQ CP KC Q D

S J DQ CP KC Q D

S R DQ CP SC Q D

MR1 2 MR2 3 NC 4 VCC 5 MS1 6

CP0

1

CP1 MR1 MR2

2 12 3 9 8 11MS2 7 Q3

Q0

Q1

Q2 = PIN NUMBERS VCC = PIN 5 GND = PIN 10

NC = NO INTERNAL CONNECTION
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

LOGIC DIAGRAM LS92

CONNECTION DIAGRAM DIP (TOP VIEW)
CP1 1 14 CP0 13 NC 12 Q0 11 Q1 10 GND 9 Q2 8 Q3

CP0

14

J

Q

J

Q

J

Q

J

Q

NC 2 NC 3 NC 4 VCC 5 MR1 6

CP KC Q D1

CP KC Q D

CP KC Q D

CP KC Q D

CP1
6

MR1 MR2

12 7

11

9

8

MR2 7 Q3

Q0

Q1

Q2

NC = NO INTERNAL CONNECTION = PIN NUMBERS VCC = PIN 5 GND = PIN 10
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

LOGIC DIAGRAM LS93

CONNECTION DIAGRAM DIP (TOP VIEW)
CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2CP0

14

J CP

Q

J CP

Q

J CP

Q

J CP

Q

MR1 2 MR2 3 NC 4 VCC 5 NC 6

KC Q D
1

KC Q D

KC Q D

KC Q D

CP1 MR1 MR2
2 12 3 9 8 11

Q0

Q1

Q2

Q3 = PIN NUMBERS VCC = PIN 5 GND = PIN 10

NC 7

NC = NO INTERNAL CONNECTION
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

FAST AND LS TTL DATA 5-91...