74Ls374

SN74LS373 SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
http://onsemi.com

The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup timesis
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 ismanufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.

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•
•
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LOW
POWER
SCHOTTKY

20

Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
InputClamp Diodes Limit High Speed Termination Effects

1

PLASTIC
N SUFFIX
CASE 738

GUARANTEED OPERATING RANGES
Symbol
VCC

Parameter
Supply Voltage

20

Min

Typ

Max

Unit

4.75

5.0

5.25

V

0

25

70

°C

TA

Operating Ambient
Temperature Range

IOH

Output Current – High

– 2.6

Output Current – Low

24

SOIC
DW SUFFIX
CASE 751D

mAIOL

1

mA

ORDERING INFORMATION
Device
SN74LS373N
SN74LS373DW
SN74LS374N
SN74LS374DW

© Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1

Package

Shipping

16 Pin DIP

1440 Units/Box

16 Pin

2500/Tape & Reel

16 Pin DIP

1440 Units/Box

16 Pin

2500/Tape & Reel

Publication Order Number:
SN74LS373/D

SN74LS373 SN74LS374CONNECTION DIAGRAM DIP (TOP VIEW)
SN74LS374

SN74LS373
VCC

O7

D7

D6

O6

O5

D5

D4

O4

LE

VCC

O7

D7

D6

O6

O5

D5

D4

O4

CP

20

19

18

17

16

15

14

13

12

11

20

19

18

17

16

15

14

13

12

11

1
OE

2
O0

3
D0

4
D1

5
O1

6
O2

7
D2

8
D3

9
O3

10
GND

1
OE

2O0

3
D0

4
D1

5
O1

6
O2

7
D2

8
D3

9
O3

10
GND

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

LOADING (Note a)
HIGH

PIN NAMES
D0 – D7
LE
CP
OE
O0 – O7

Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs

LOW

0.5 U.L.0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.

0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.

NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

TRUTH TABLE
LS373

LS374

Dn

LE

OE

On

Dn

H

H

L

H

H

L

H

L

L

L

L

Q0

X

X

X

H

Z*

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note:Contents of flip-flops unaffected by the state of the Output Enable input (OE).

http://onsemi.com
2

OE

On

L

L

X

LE

H

L
X

L

H

Z*

SN74LS373 SN74LS374
LOGIC DIAGRAMS
SN74LS373

3

4

D0

D1
D

D2
D

Q
G

LATCH
ENABLE
LE
11

8

7

13

D3

D
Q
G

14

D4
D

Q
G

17

D5
D

Q
G

18

D6

D
Q
G

VCC = PIN 20GND = PIN 10
= PIN NUMBERS

D7
D

Q
G

D
Q
G

Q
G

OE

1

O1

O0

O2

5

2

O3
9

6

O4

O5

12

O6
16

15

O7
19

SN74LS374
3

4

D0

11

7

D1

8

D2

13

D3

14

D4

17

18

D5

D6

D7

CP
CP D
QQ

CP D
QQ

CP D
QQ

CP D
QQ

CP D
QQ

CP D
QQ

CP D
QQ

CP D
QQ

OE
1

O0
2

O1
5...