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Publicado: 23 de noviembre de 2010
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zx1 mio External Reference Specification
zx1 mio
(Memory and I/O)
External Reference Specification
Revision 1.0 03/27/03
Page 1 of 57
H
1
zx1 mio External Reference Specification
OPERATION OVERVIEW ..................................................................... 4
1.1 zx1-basedSystems........................................................................................................... 4 1.2 zx1 mio’s Major Blocks .................................................................................................. 5 1.2.1 Itanium-2 bus interface block (BIB)........................................................................ 6 1.2.2 Memory Controller (MC) ........................................................................................ 6 1.2.3I/O Cache Controller (IOCC) .................................................................................. 6 1.2.4 Rope-quad Controller (RQC) .................................................................................. 6 1.3 zx1 mio Interconnect ....................................................................................................... 7 1.3.1 Itanium-2 Bus.......................................................................................................... 7 1.3.2 I/O Ropes................................................................................................................. 7 1.3.3 PDH Bus.................................................................................................................. 7 1.4 Terminology.................................................................................................................... 8 1.4.1 Device Terminology................................................................................................ 8 1.4.2 Cache State Terminology ........................................................................................ 8 1.4.3 Address SpaceTerminology.................................................................................... 8 1.4.4 Transaction Terminology ........................................................................................ 9 1.4.5 Other Terminology ................................................................................................ 11
2
System Address Map..............................................................................12
2.1 zx1 mio Physical Address Map ..................................................................................... 12 2.2 The Compatibility Hole (640K to 1M).......................................................................... 13 2.2.1 BIOS shadowing / write–protect ........................................................................... 14 2.2.2 VGA support......................................................................................................... 14 2.2.3 ISA aliases ............................................................................................................. 15 2.3 MMIO above 4 GB........................................................................................................ 17 2.4 I/O port space................................................................................................................ 18 2.4.1 Itanium-2 I/O Port Space....................................................................................... 18 2.4.2 LMMIO I/O Port Space......................................................................................... 18 2.4.3 GMMIO I/O Port Space........................................................................................ 19 2.4.4 Summary of I/O Port Spaces ................................................................................. 20 2.5 Range register programming ......................................................................................... 20 2.5.1 Range registers for the compatibility hole............................................................. 20 2.5.2...
zx1 mio External Reference Specification
zx1 mio
(Memory and I/O)
External Reference Specification
Revision 1.0 03/27/03
Page 1 of 57
H
1
zx1 mio External Reference Specification
OPERATION OVERVIEW ..................................................................... 4
1.1 zx1-basedSystems........................................................................................................... 4 1.2 zx1 mio’s Major Blocks .................................................................................................. 5 1.2.1 Itanium-2 bus interface block (BIB)........................................................................ 6 1.2.2 Memory Controller (MC) ........................................................................................ 6 1.2.3I/O Cache Controller (IOCC) .................................................................................. 6 1.2.4 Rope-quad Controller (RQC) .................................................................................. 6 1.3 zx1 mio Interconnect ....................................................................................................... 7 1.3.1 Itanium-2 Bus.......................................................................................................... 7 1.3.2 I/O Ropes................................................................................................................. 7 1.3.3 PDH Bus.................................................................................................................. 7 1.4 Terminology.................................................................................................................... 8 1.4.1 Device Terminology................................................................................................ 8 1.4.2 Cache State Terminology ........................................................................................ 8 1.4.3 Address SpaceTerminology.................................................................................... 8 1.4.4 Transaction Terminology ........................................................................................ 9 1.4.5 Other Terminology ................................................................................................ 11
2
System Address Map..............................................................................12
2.1 zx1 mio Physical Address Map ..................................................................................... 12 2.2 The Compatibility Hole (640K to 1M).......................................................................... 13 2.2.1 BIOS shadowing / write–protect ........................................................................... 14 2.2.2 VGA support......................................................................................................... 14 2.2.3 ISA aliases ............................................................................................................. 15 2.3 MMIO above 4 GB........................................................................................................ 17 2.4 I/O port space................................................................................................................ 18 2.4.1 Itanium-2 I/O Port Space....................................................................................... 18 2.4.2 LMMIO I/O Port Space......................................................................................... 18 2.4.3 GMMIO I/O Port Space........................................................................................ 19 2.4.4 Summary of I/O Port Spaces ................................................................................. 20 2.5 Range register programming ......................................................................................... 20 2.5.1 Range registers for the compatibility hole............................................................. 20 2.5.2...
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