Capacitores De Desacople

HOW TO CHOOSE & PLACE DECOUPLING CAPACITORS TO REDUCE THE COST OF THE ELECTRONIC PRODUCTS

Zhen Mu and Heiko Dudek Cadence Design Systems, Inc. Kun Zhang Huawei Technologies Co., Ltd.

With the edge rates of high-speed signals on boards increasing dramatically in modern PCB designs, it becomes more challenging to manage clean power supplies. The number of decoupling capacitors used for apower delivery system keeps increasing as well. This causes two problems for board designers and layout engineers: 1) How to determine the numbers and the types of decoupling capacitors needed for a particular design; and 2) Where to place the selected capacitors on board. Without a clear set of tools and methodologies to solve these two problems, many boards would have to be treated in a pessimisticand conservative way and would end up with a lot of unnecessary decoupling capacitors, which increases design cost, reduces board reliability, and also makes it extremely difficult to place and route capacitors in a limited board space.
This paper provides a solution for board designers to choose decoupling capacitors early in the design process. It illustrates how it is not a good practice toplace decoupling capacitors with fixed values at every pin of a chip with the fastest switching speed. The method described in this paper shows how a more effective decoupling can be achieved with fewer decoupling capacitors. A real design example will be given to show the savings on capacitors and board space when applying such a selection method. The paper

also presents the case that it is notalways necessary to place these capacitors close to the power pins of the ICs that the capacitors are designated to associate with. The actual distance of the decoupling capacitor from the power pin varies based on the value and other characteristics of the decoupling capacitor DESIGNING POWER DELIVERY SYSTEMS Using target impedance to describe the behavior of a power delivery system has beenwidely accepted. Considering the voltage ripple budget when worst transient current occurs, target impedance has been defined as follows [1

Zt arg et

( power _ sup ply _ voltage) (allowed _ ripple) current

For reliable operation of a power delivery system, its impedance spectrum needs to be maintained below the target impedance at the frequencies from DC to fmax. The fmax can be evaluatedaccording to the edge rate of the fastest chip powered by the power supply [1].

Due to the scales of ICs, packages and board, larger values of decoupling capacitors on a board work at lower frequency range. In addition, smaller package and die capacitance is effective in the higher frequency range, and plane capacitance dominates at even higher frequencies. It is important to understand this andto look at each frequency band independently.

Based on this understanding, decoupling capacitors can be chosen first without taking into account the effects of power and ground planes. For example, the blue trace in Figure 1 shows the frequency responses of a general plane pair. The first serial resonance peak (lowest resonance frequency point which is based on the size of a regular shapedplane) does not occur until the frequency reaches f0. To keep the distributed impedance of a power delivery system below the target impedance, decoupling capacitors are needed in the frequency range from DC to fd. If decoupling capacitors are correctly selected, the actual response becomes what is shown as red in Figure 1. The overall distributed impedance from DC to f0 is kept under the targetimpedance, while the first resonance frequency peak of the plane remains almost un-changed. This shows that, in general, we can design the power delivery systems with two separated steps. When the physical size of a plane is large enough, its lowest resonant frequency can fall into the effective ranges of small values of decoupling capacitors. Then, these capacitors need to be carefully selected to...