Circuito 7493

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

March 1998

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is lowthe slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is high the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is high. Datatransfers to the outputs on the falling edge of the clock pulse. A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.

Features
n Alternate Military/Aerospace device (5473) is available. Contact a Fairchild Semiconductor Sales Office/Distributor for specifications.

Connection Diagram
Dual-In-Line Package

DS006525-1

Order Number5473DMQB, 5473FMQB, DM5473J, DM5473W or DM7473N See Package Number J14A, N14A or W14B

Function Table
Inputs CLR L H H H H CLK X
I I I I

Outputs J X L H L H K X L L H H Q L Q0 H L Toggle Q H Q0 L H

H = High Logic Level L = Low Logic Level X = Either Low or High Logic Level I = Positive pulse data. the J and K inputs must be held constant while the clock is high. Data is transferred to theoutputs on the falling edge of the clock pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each high level clock pulse.

© 1998 Fairchild Semiconductor Corporation

DS006525

www.fairchildsemi.com

Absolute Maximum Ratings (Note 1)
Supply Voltage Input Voltage Operating Free AirTemperature Range 7V 5.5V

DM54 and 54 DM74 Storage Temperature Range

−55˚C to +125˚C 0˚C to +70˚C −65˚C to +150˚C

Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 6) Pulse Width (Note 6) tSU tH TA Clock High Clock LowClear Low Input Setup Time (Notes 2, 6) Input Hold Time (Notes 2, 6) Free Air Operating Temperature 0 20 47 25 0↑ 0↓ −55 125 4.5 2 0.8 −0.4 16 15 0 20 47 25 0↑ 0↓ 0 70 ns ns ˚C ns DM5473 Nom 5 Max 5.5 Min 4.75 2 0.8 −0.4 16 15 DM7473 Nom 5 Max 5.25 V V V mA mA MHz Units

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The deviceshould not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIHParameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current @ Max Input Voltage High Level Input Current IIL Low Level Input Current IOS ICC Short Circuit Output Current Supply Current VCC = Max VI = 2.4V VCC = Max VI = 0.4V VCC = Max J, K Clock Clear J, K Clock Clear DM54 −20 −18 18 (Note 4) DM74 VCC = Max, (Note 5) 40 80 80 −1.6 −3.2 −3.2 −55 −55 34 mA mA mA µAConditions VCC = Min, II = −12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V Min Typ (Note 3) −1.5 2.4 3.4 0.2 0.4 1 V V V mA Max Units

Note 2: The symbol (↑, ↓) indicates the edge of the clock pulse is used for reference: (↑) for rising edge, (↓) for falling edge. Note 3: All typicals are at VCC = 5V, TA = 25˚C. Note 4: Not more...