Cmos
1 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
Outline
The CMOS inverter Logic Gates Digital circuits
Note: some slides are taken from Dr. Paulo Moreira’s presentation in the course “MICROPROCESSOR LABORATORY SECOND CENTRAL AMERICAN REGIONAL COURSE ON ADVANCED VLSI DESIGN TECHNIQUES”, Puebla – Mexico, 29 November - 17 December 2004. Anotherfigures are taken from R. J. Baker et al., CMOS: Circuit Design, Layout, and Simulation, Wiley Interscience, 1998
2 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
part 1: CMOS Inverter
3 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
A masterpiece
• Logic levels • MOSFET – a simple switch • The CMOS inverter:
– – – – – DC operation Dynamicoperation Propagation delay Power consumption Layout
4 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
CMOS logic: “0” and “1”
• Logic circuits process Boolean variables • Logic values are associated with voltage levels:
– VIN > VIH ⇒ “1” – VIN < VIL ⇒ “0”
Output +V "1" VOH
Noise Margin High
Input +V
VIH
Undefined region
• Noise margin:
– NMH=VOH-VIH –NML=VIL-VOL
VOL "0" 0
VIL
Noise Margin Low
0
5 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
The CMOS inverter
DC Characteristics
6 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
The MOSFET - a simple switch
p-switch S B A p-switch G A 0 0 1 1 B 0 1 0 1 Y bad 0 (source follower) good 1 ? (high Z) ? (high Z)
D n-switch DY Y
A n-switch G A 0 0 1 1
B 0 1 0 1
Y ? (high Z) ? (high Z) good 0 bad 1 (source follower)
S
B
7 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
The CMOS inverter
VDD VDD p-switch
A Y 0 1
Y good 1 good 0
A
Y
A n-switch
VSS
VSS
8
E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
The CMOS inverterRegions of operation (balanced inverter):
Vin 0 VTNVdd/2 Vdd n-MOS cut-off saturation saturation linear linear p-MOS linear linear saturation saturation cut-off Vout Vdd ~Vdd Vdd/2 ~0 0
9 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
Switching Characteristics
Inverter transient response
3 2.5
Vout, Vin (V)
2 1.5 1 0.5 0 -0.5
Vout
Vin 0 2 4 6 Time(ns) 8
CL=250fF
10 12
0.6
(mA)
0.4 0.2 0 -0.2 -0.4 -0.6
I D(nmos)
CL=250fF
ID
I D(pmos) 0 2 4 6 Time (ns) 8 10 12
10 E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
Sizing the CMOS inverter
β = µCox ⎜
E. Martinez-Guerrero /Taller de Diseño Físico/MDE_DESI_ITESO/Otoño_2006
⎛W ⎝L
⎞ ⎛W ⎞ = kn, p ⎜ ⎟ ⎟ ⎠ ⎝L⎠
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Design parametersof CMOS inverter
• Propagation delay
– Main origin: load capacitance
t pLH = t pHL = k p (Vdd − VTP ) k n (Vdd − VTN C L ⋅ Vdd C L ⋅ Vdd
2
≈ ≈
CL k p ⋅ Vdd
)2
CL k n ⋅ Vdd ⎛ 1 1⎞ ⎜ + ⎟ ⎝ kn k p ⎠
CL 1 t p ≈ t pLH + t pLH = 2 2 ⋅ Vdd
(
)
– To reduce the delay:
• Reduce CL • Increase kn and kp. That is, increase W/L
12 E. Martinez-Guerrero /Taller de DiseñoFísico/MDE_DESI_ITESO/Otoño_2006
CMOS power budget
– Dynamic power consumption:
• Charging and discharging of capacitors
– Short circuit currents:
• Short circuit path between power rails during switching
– Leakage
• Leaking diodes. • Leaking transistors:
– Sub-threshold currents – In the future devices gate leakage current!?
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Dynamic power dissipation
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Design parameters of CMOS inverter
• The dynamic power dissipation is a function of:
– Frequency – Capacitive loading – Voltage swing
•
To reduce dynamic power dissipation
– Reduce: CL – Reduce: f – Reduce: Vdd ⇐ The most effective action
Dynamic power VDD
CMOS...
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