Communicatons

A FPGA-based 5 Gbit/s D-QPSK Modem
Master of Science Thesis

WEN WU
Department of Signals and Systems Division of Communications Systems CHALMERS UNIVERSITY OF TECHNOLOGY Göteborg, Sweden, 2011 Report No. EX014/2010

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Chalmers Masters Thesis 2010-Nov

Number: EX014/2010

Master Thesis: A FPGA-based 5 Gbit/s D-QPSK Modem

Wen
 Wu
  Chalmers University
 of
 Technology
 
  Department
 of
 Signal
 and
 System
 

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Chalmers Masters Thesis 2010-Nov

Number: EX014/2010

Abstract:
E-band (71-76 GHz and 81-86 GHz) is permitted worldwide for ultra high capacity point-to-point (P2P) communications. The 10 GHz spectrum represents by far the widest bandwidth ever allocated for radio P2P links,enabling fibre-like transmission with data rates of gigabit per second (Gbps) and greater that are difficult to reach using the bandwidth-limited, lower microwave frequency bands. The goal of this project is to develop a Differential Quadrature Phase Shift Keying (D-QPSK) modem supporting 5 Gbps (Gigabits per second) data rate transmission. A 2.5 Gbps fieldprogrammable gate array (FPGA)-based modemhad been designed and verified previously. This modem was built using FPGA and microwave components, in which the FPGA is programmed to generate a D-QPSK signal and the microwave components perform the up-and down-conversion between baseband and intermediate frequency (IF) signal. However, it is not a trivial task at all to upgrade the modem to 5 Gbps, since there are severe limitations with theFPGA solution to support the required data rate. In this thesis, a prefix parallel layer (PPL) algorithm is proposed to increase the speed of differential coding process. This algorithm can be implemented in a FPGA and it is capable for processing data rate of 5 Gbps and higher. In addition, the demodulator structure is simplified, which also raise the capability of detecting higher data rateD-QPSK signal. The 5 Gbps D-QPSK is tested the in lab environment and at the end of the project the system has successfully achieved error-free transmission. However, improvements in several aspects are needed to turn this proof-of-concept experiment into prototype for products.

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Index
 
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ABSTRACT: INDEX ACKNOWLEDGMENT 1
  INTRODUCTION 1.1
  1.2
  1.3
  2
  2.1
  2.2
  3
  3.1
  3.2
  3.3
 3.4
  4
  PROJECT BACKGROUND PROJECT OUTLINE THESIS REPORT OUTLINE WHY D-QPSK? D-QPSK CODING RULE FPGA-BASED IMPLEMENTATION INTRODUCTION FPGA WITH HIGH SPEED INTERFACE FPGA KITS USED IN THIS PROJECT FPGA DEVELOPMENT WORKFLOW

D-QPSK MODULATION FUNDAMENTAL

FIELD- PROGRAMMABLE GATE ARRAY (FPGA)

MODEM IMPLEMENTATION 4.1
  MODULATOR 4.1.1
  Conventional modulator architecture 4.1.2  FPGA based Modulator 4.2
  D-QPSK CODING ALGORITHM 4.2.1
  Previous coding algorithm 4.2.2
  Improved algorithm 4.3
  DEMODULATOR 4.3.1
  Demodulator architecture 4.3.2
  Limitation for upgrading to 5 Gbps 4.3.3
  Improved demodulator structure 4.3.4
  FPGA based 2:1 MUX

5
 

TEST RESULT 5.1
  TEST BENCH SETUP 5.2
  TIME DOMAIN MEASUREMENT 5.2.1
 FPGA output signal quality 5.2.2
  The waveform of the demodulator 5.3
  FREQUENCY DOMAIN MEASUREMENT 5.4
  THE FPGA RESOURCES UTILIZATION

6
 

DISCUSSION

REFERENCE

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Chalmers Masters Thesis 2010-Nov

Number: EX014/2010

Acknowledgment
First, I would like to thank Dr. Yinggang Li who gave me the chance to join Ericsson and participate in this...