Datasheet
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Publicado: 24 de octubre de 2011
MC9S08SE8 MC9S08SE4
Reference Manual
Related Documentation:
• MC9S08SE8 (Data Sheet) Contains pin assignments and diagrams, all electrical specifications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com
HCS08 Microcontrollers
MC9S08SE8RM Rev. 3 4/2009
freescale.com
MC9S08SE8 Features
8-Bit HCS08 Central Processor Unit(CPU)
•
• • • •
20 MHz HCS08 CPU (central processor unit) 10 MHz internal bus frequency HC08 instruction set with added BGND Support for up to 32 interrupt/reset sources
•
On-Chip Memory
•
•
Up to 8 KB of on-chip in-circuit programmable flash memory with block protection and security options Up to 512 bytes of on-chip RAM
Power-Saving Modes Clock Source Options
• •ADC — 10-channel, 10-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; runs in stop3 TPMx — One 2-channel (TPM1) and one 1-channel (TPM2) 16-bit timer/pulse-width modulator (TPM) modules; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured forbuffered, centered PWM (CPWM) on all channels KBI — 8-pin keyboard interrupt module RTC — Real-time counter with binary- or decimal-based prescaler
Input/Output
•
•
Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Internal Clock Source (ICS) — Internal clock source module containing afrequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz.
• • • • •
Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength on portswhen used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost
Package Options
System Protection
•
Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock
• • •
28-pin PDIP 28-pin SOIC 16-pin TSSOP
Development Support
•Single-wire background debug interface
Peripherals
•
SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge
MC9S08SE8 MCU Series Reference Manual
Covers: MC9S08SE8 MC9S08SE4
MC9S08SE8 Rev. 3 4/2009
Revision History
To provide the most up-to-date information, the revision of our documents on theWorld Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document.
Revision Number
1 2 3
Revision Date
9/22/2008 12/12/2008 4/7/2009 Initial public released.
Description of Changes
Changed the MCGat 0xFFAF in Table 4-4 to ICS. Modified some typos. Updated Figure 4-2 and Figure 4-3. In Chapter 10, “Internal Clock Source (S08ICSV3),” added a note in Section 10.1.4.7, “Stop (STOP);” updated Figure 10-2 to reflect ICSERCLK is gated off when STOP is high or when ERCLKEN is low.
This product incorporates SuperFlash® technology licensed from SST. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
MC9S08SE8 MCU Series Reference Manual, Rev. 3 6 Freescale Semiconductor
List of Chapters
Chapter Number Title Page Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . ....
Reference Manual
Related Documentation:
• MC9S08SE8 (Data Sheet) Contains pin assignments and diagrams, all electrical specifications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com
HCS08 Microcontrollers
MC9S08SE8RM Rev. 3 4/2009
freescale.com
MC9S08SE8 Features
8-Bit HCS08 Central Processor Unit(CPU)
•
• • • •
20 MHz HCS08 CPU (central processor unit) 10 MHz internal bus frequency HC08 instruction set with added BGND Support for up to 32 interrupt/reset sources
•
On-Chip Memory
•
•
Up to 8 KB of on-chip in-circuit programmable flash memory with block protection and security options Up to 512 bytes of on-chip RAM
Power-Saving Modes Clock Source Options
• •ADC — 10-channel, 10-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; runs in stop3 TPMx — One 2-channel (TPM1) and one 1-channel (TPM2) 16-bit timer/pulse-width modulator (TPM) modules; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured forbuffered, centered PWM (CPWM) on all channels KBI — 8-pin keyboard interrupt module RTC — Real-time counter with binary- or decimal-based prescaler
Input/Output
•
•
Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Internal Clock Source (ICS) — Internal clock source module containing afrequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz.
• • • • •
Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength on portswhen used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost
Package Options
System Protection
•
Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock
• • •
28-pin PDIP 28-pin SOIC 16-pin TSSOP
Development Support
•Single-wire background debug interface
Peripherals
•
SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge
MC9S08SE8 MCU Series Reference Manual
Covers: MC9S08SE8 MC9S08SE4
MC9S08SE8 Rev. 3 4/2009
Revision History
To provide the most up-to-date information, the revision of our documents on theWorld Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document.
Revision Number
1 2 3
Revision Date
9/22/2008 12/12/2008 4/7/2009 Initial public released.
Description of Changes
Changed the MCGat 0xFFAF in Table 4-4 to ICS. Modified some typos. Updated Figure 4-2 and Figure 4-3. In Chapter 10, “Internal Clock Source (S08ICSV3),” added a note in Section 10.1.4.7, “Stop (STOP);” updated Figure 10-2 to reflect ICSERCLK is gated off when STOP is high or when ERCLKEN is low.
This product incorporates SuperFlash® technology licensed from SST. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
MC9S08SE8 MCU Series Reference Manual, Rev. 3 6 Freescale Semiconductor
List of Chapters
Chapter Number Title Page Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . ....
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