Datashet

UTC 4053

CMOS IC

ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
DESCRIPTION
SOP-16

The UTC 4053 are Triple SPDT analog multiplexers for
application as digitally–controlled analog switches.

FEATURES
DIP-16

* Analog Voltage Range (VDD – VEE) = 3.0 ~ 18 V
Note: VEE must be≦VSS
* Linearized Transfer Characteristics
* Pin–to–Pin Replacement for CD4053

TSSOP-16

*Pb-free plating productnumber: 4053L

PIN CONFIGURATIONS

Y1

16

V DD

Y0

2

15

Y

Z1

3

14

X

Z

4

13

X1

Z0

5

12

X0

INH

6

11

A

V EE

7

10

B

V SS

UTC

1

8

9

C

UTC 4053

UNISONIC TECHNOLOGIES

www.unisonic.com.tw

CO., LTD.

1
QW-R502-036,A

UTC 4053

CMOS IC

UTC 4053 Triple 2–Channel AnalogMultiplexer/Demultiplexer

CONTROLS

SWITCHES
IN/OUT

6
11
10
9
12
13
2
1
5
3

INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1

14

15

COMMONS
OUT/IN

4

VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be≦VSS.

ABSOLUTE MAXIMUM RATINGS*
PARAMETER
DC Supply Voltage (Referenced to VEE, VSS≧VEE)SYMBOL
VDD

RATINGS
-0.5 ~ +18.0

Input or Output Voltage (DC or Transient) (Referenced to VSS
Vin, Vout
for Control Inputs and VEE for Switch I/O)
Input Current (DC or Transient), per Control Pin
Iin
Switch Through Current
ISW
Power Dissipation. Per Package**
PD
Storage Temperature
Tstg
Lead Temperature (8 - Second Soldering)
TLead
* Maximum Ratings are those values beyond whichdamage to the device may occur.
** Temperature Derating: “DIP and SOP” Packages: – 7.0 mW/℃ From 65℃ ~ 125℃

UNIT
V

-0.5 ~ VDD +0.5

V

±10
±25
500
-65 ~ +150
260

mA
mA
mW
℃
℃

ELECTRICAL CHARACTERISTICS
(Ta=25℃, unless otherwise indicated.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP#
MAX UNIT
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
VDD – 3.0≧VSS≧VEE
3.018
V
Power Supply Voltage Range
VDD
Control Inputs: Vin = VSS or VDD
Switch I/O: VEE ≦VI/O ≦VDD,
and ∆Vswitch≦500mV*
Quiescent Current per Package
IDD
µA
VDD=5.0V
0.005
5.0
VDD=10V
0.010
10
VDD=15V
0.015
20
Ta=25℃ only (The channel
component, (Vin - Vout)/Ron, is
not included.)
Total Supply Current (Dynamic Plus
ID(AV)
µA
VDD=5.0V
Quiescent, Per Package)
(0.07 µA/kHz) f+ IDD Typical
VDD=10V
(0.20 µA/kHz) f + IDD
VDD=15V
(0.36 µA/kHz) f + IDD

UTC

UNISONIC TECHNOLOGIES

www.unisonic.com.tw

CO., LTD.

2
QW-R502-036,A

UTC 4053

CMOS IC

PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP#
MAX UNIT
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to VSS)
Ron= per spec, Ioff = per spec
VDD=5.0V
2.25
1.5
Low – Level Input Voltage
VIL
VVDD=10V
4.50
3.0
VDD=15V
6.75
4.0
Ron= per spec, Ioff = per spec
VDD=5.0V
3.5
2.75
High – Level Input Voltage
VIH
V
VDD=10V
7.0
5.50
VDD=15V
11
8.25
Input Leakage Current
Iin
Vin= 0 or VDD, VDD=15V
±0.00001 ±0.1
µA
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE)
Recommended Peak–to–Peak Voltage
Channel Onor Off
VI/O
0
VDD
VPP
Into or Out of the Switch
Recommended Static or Dynamic
Channel On
∆Vswitch
0
600
mV
Voltage Across the Switch** (Figure 3)
Output Offset Voltage
VOO
Vin = 0V, No Load
10
µV
∆Vswitch≦500mV*
Vin = VIL or VIH (Control), and
Vin = 0 to VDD (Switch)
ON Resistance
Ron
Ω
VDD=5.0V
250
1050
VDD=10V
120
500
VDD=15V
80
280
VDD=5.0V
25
70
ΔONResistance Between Any Two
∆Ron
VDD=10V
10
50
Ω
Channels in the Same Package
VDD=15V
10
45
Vin = VIL or VIH (Control)
Off–Channel Leakage Current
Channel to Channel or Any
Ioff
±0.05
±100
nA
(Figure 8)
One Channel, VDD=15V
Capacitance, Switch I/O
CI/O
Inhibit = VDD
10
pF
Capacitance, Common O/I
CO/I
Inhibit = VDD
17
pF
Capacitance, Feedthrough
Pins Not Adjacent
0.15
CI/O...