Diodo

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

D Package Options Include Plastic
Small-Outline (D, NS, PS), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN5400 . . . J PACKAGE SN54LS00, SN54S00 . . . J OR W PACKAGESN7400, SN74S00 . . . D, N, OR NS PACKAGE SN74LS00 . . . D, DB, N, OR NS PACKAGE (TOP VIEW)

D Also Available as Dual 2-Input
Positive-NAND Gate in Small-Outline (PS) Package

SN74LS00, SN74S00 . . . PS PACKAGE (TOP VIEW)

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 4B 4A 4Y 3B 3A 3Y

1A 1B 1Y GND

1 2 3 4

8 7 6 5

VCC 2B 2A 2Y

SN5400 . . . W PACKAGE (TOPVIEW)

SN54LS00, SN54S00 . . . FK PACKAGE (TOP VIEW)

1A 1B 1Y VCC 2Y 2A 2B

1 2 3 4 5 6 7

14 13 12 11 10 9 8

4Y 4B 4A GND 3B 3A 3Y

1B 1A NC VCC 4B 1Y NC 2A NC 2B
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13

4A NC 4Y NC 3B

NC − No internal connection

description/ordering information
These devices contain four independent 2-input NAND gates. The devices perform theBoolean function Y = A • B or Y = A + B in positive logic.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the termsof Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

2Y GND NC 3Y 3A
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Copyright  2003,Texas Instruments Incorporated

1

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
description/ordering information (continued)
ORDERING INFORMATION
TA PACKAGE† ORDERABLE PART NUMBER SN7400N PDIP − N Tube Tube Tape and reel Tube SOIC − D 0 C 70 C 0°C to 70°C Tape and reel Tube Tape and reelSN74LS00N SN74S00N SN7400D SN7400DR SN74LS00D SN74LS00DR SN74S00D SN74S00DR SN7400NSR SOP − NS Tape and reel SN74LS00NSR SN74S00NSR SN74LS00PSR SOP − PS SSOP − DB Tape and reel Tape and reel SN74S00PSR SN74LS00DBR SNJ5400J CDIP − J Tube SNJ54LS00J SNJ54S00J SNJ5400W −55°C to 125°C CFP − W Tube SNJ54LS00W SNJ54S00W SNJ54LS00FK LCCC − FK Tube SNJ54S00FK S00 SN7400 74LS00 74S00 LS00 S00 LS00 SNJ5400JSNJ54LS00J SNJ54S00J SNJ5400W SNJ54LS00W SNJ54S00W SNJ54LS00FK SNJ54S00FK LS00 7400 TOP-SIDE MARKING SN7400N SN74LS00N SN74S00N

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H

logic diagram, each gate (positive logic)
A B Y

2

POSTOFFICE BOX 655303

• DALLAS, TEXAS 75265

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

schematic
’00 VCC 4 kΩ 1.6 kΩ 130 Ω

A B

Y

1 kΩ GND

’LS00 VCC 20 kΩ 8 kΩ 120 Ω 2.8 kΩ

’S00 VCC 900 Ω 50 Ω

A 3.5 kΩ B 12 kΩ 4 kΩ Y A B Y

500 Ω

250 Ω

1.5 kΩ

3 kΩ GND

GNDResistor values shown are nominal.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

3

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . ....