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Páginas: 15 (3615 palabras) Publicado: 21 de noviembre de 2012
Features
• Fast Read Access Time – 150 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes

• Fast Write Cycle Times









– Page Write Cycle Time: 10 ms Maximum
– 1 to 64-byte Page Write Operation
Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling and ToggleBit for End of Write Detection
High Reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges

Description
The AT28C64B is a high-performance electrically-erasable and programmable read
only memory (EEPROM). Its 64K ofmemory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 150 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
(continued)

Pin Configurations
Function

A0 - A12

Addresses

CE

Chip Enable

OE

Output Enable

WE

WriteEnable

I/O0 - I/O7

Data Inputs/Outputs

NC

No Connect

DC

Don’t Connect

NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND

PLCC
Top View

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5

Note:

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VCC
WE
NC
A8
A9
A11OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

TSOP
Top View

A7
A12
NC
DC
VCC
WE
NC
4
3
2
1
32
31
30

29
28
27
26
25
24
23
22
21

14
15
16
17
18
19
20

5
6
7
8
9
10
11
12
13

AT28C64B

PDIP, SOIC
Top View

Pin Name

A6
A5
A4
A3
A2
A1
A0
NC
I/O0

64K (8K x 8)
Parallel
EEPROM with
Page Write and
Software Data
Protection

PLCCpackage pins 1 and 17 are
DON’T CONNECT.

OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

Rev. 0270H–12/99

1

The AT28C64B is accessed like a Static RAM for the read
or write cycle without the needfor external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.
Theend of a write cycle can be detected by DATA POLLING of I/O 7 . Once the end of a write cycle has been
detected, a new access for a read or write can begin.

Atmel’s AT28C64B has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protectionmechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
withRespect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V

2

AT28C64B

*NOTICE:

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is...
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