Dspic30f6010a

dsPIC30F6010A/6015
dsPIC30F6010A/6015 Rev. A2 Silicon Errata
The dsPIC30F6010A/6015 (Rev. A2) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70150 – “dsPIC30F6010A/6015 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” The exceptions to thespecifications in the documents listed above are described in this section. These exceptions are described for the specific devices listed below: • dsPIC30F6010A • dsPIC30F6015 These devices may be identified by the following message that appears in the MPLAB® ICD 2 Output Window under MPLAB IDE, when a “Reset and Connect” operation is performed within MPLAB IDE:
Setting Vdd source to target TargetDevice dsPIC30F6010A found, revision = Rev A2 ...Reading ICD Product ID Running ICD Self Test ...Passed MPLAB ICD 2 Ready

Silicon Errata Summary
The following list summarizes the errata described in this document: 1. DISI Instruction The DISI instruction will not disable interrupts if DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero. 2.Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 3. Output Compare Module in PWM Mode Output compare will produce a glitch when loading 0% duty cycle in PWM mode. It will also miss the next compare after the glitch. 4. Quadrature Encoder Interface Module TheIndex Pulse Reset mode of the QEI does not work properly when used along with count error detection. When counting upwards, the POSCNT register will increment one extra count after the index pulse is received. The extra count will generate a false count error interrupt. 5. INT0, ADC and Sleep Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits arenon-zero. 6. 10-bit ADC: Sampling Rate The 10-bit Analog-to-Digital Converter (ADC) has a maximum sampling rate of 750 ksps. 7. Quadrature Encoder Interface (QEI) Module The QEI module does not generate an interrupt in a particular overflow condition. 8. Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The currentconsumption during Sleep may also increase beyond the specifications listed in the device data sheet.

The errata described in this section will be addressed in future revisions of dsPIC30F6010A and dsPIC30F6015 devices.

© 2008 Microchip Technology Inc.

DS80258F-page 1

dsPIC30F6010A/6015
9. I2C™ Module When the I2C module is enabled, the dsPIC® DSC device generates a glitch on the SDAand SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. 10. I2C Module The I2C module loses incoming data bytes when operating as an I2C slave. 11. Motor Control PWM – PWM Counter Register PTMR does not continue counting down after halting code execution in Debug mode. 12. I/O Port – Port Pin Multiplexed with IC1 Theport I/O pin multiplexed with the Input Capture 1 (IC1) function cannot be used as a digital input pin when the UART auto-baud feature is enabled. 13. I2C Module After enabling the I2C module (I2CEN = 1), the S and P bit values are not correct. 14. I2C Module: 10-bit addressing mode When the I2C module is configured for 10-bit addressing using the same address bits (A10 and A9) as other I2C deviceA10 and A9 bits may not work as expected. 15. Timer Module Clock switching prevents the device from waking up from Sleep. The following sections describe the errata and work around to these errata, where they may apply.

DS80258F-page 2

© 2008 Microchip Technology Inc.

dsPIC30F6010A/6015
1. Module: DISI Instruction
When a user executes a DISI #7, for example, this will disable...