Electro

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

August 1986 Revised March 2000

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data isprocessed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clearinput will reset the outputs regardless of the levels of the other inputs.

Ordering Code:
Order Number DM74LS73AM DM74LS73AN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffixletter “X” to the ordering code.

Connection Diagram

Function Table
Inputs CLR L H H H H H CLK X ↓ ↓ ↓ ↓ H J X L H L H X K X L L H H X Q0 Q L Q0 H L Toggle Q0 Outputs Q H Q0 L H

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↓ = Negative going edge of pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each outputchanges to the complement of its previous level on each falling edge of the clock pulse.

© 2000 Fairchild Semiconductor Corporation

DS006372

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Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0°C to +70°C −65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are thosevalues beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions
Symbol VCC VIH VIL IOHIOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) tW Pulse Width (Note 3) tSU tSU tH tH TA Clock HIGH Preset LOW Clear LOW Clock HIGH Preset LOW Clear LOW Setup Time (Note 2)(Note 4) Setup Time (Note 3)(Note 4) Hold Time (Note 2)(Note 4) Hold Time(Note 3)(Note 4) Free Air Operating Temperature 0 0 20 25 25 25 30 30 20↓ 25↓ 0↓ 5↓ 0 70 ns ns ns ns °C ns ns Parameter Min 4.75 2 0.8 −0.4 8 30 25 Nom 5 Max 5.25 Units V V V mA mA MHz MHz

Note 2: CL = 15 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.www.fairchildsemi.com

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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply CurrentConditions VCC = Min, II = −18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) J, K Clear Clock J, K Clear Clock J, K Clear Clock −20 4 2.7 3.4 0.35 0.25 0.5 0.4 0.1 0.3 0.4 20 60 80 −0.4 −0.8 −0.8 −100 6 mA mA mA µA mA Min Typ (Note 5) Max −1.5...