Especificaciones I2C V2.1
Páginas: 76 (18759 palabras)
Publicado: 24 de mayo de 2012
THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000
document order number: 9398 393 40011
Philips Semiconductors
The I2C-bus specification
CONTENTS 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 8.3 9 10 10.1 10.1.1 10.1.2 10.1.3 11 12 13 13.1 13.2 13.3 PREFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Version 1.0 - 1992. . . . . . . . . . . . . . . . . . .. Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . Purchase of Philips I2C-bus components . . 3 3 3 3 13.5.1 13.5.2 13.5.3 14 14.1 14.2 14.3 15 13.4 13.5 Hs-mode devices at lower speed modes . . 24 Mixed speed modes on one serial bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 F/S-mode transfer in amixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Hs-mode transfer in a mixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing requirements for the bridge in a mixed-speed bus system . . . . . . . . . . . . . . 27 10-BIT ADDRESSING . . . . . . . . . . . . . . . . 27 Definition of bits in the first two bytes. . . . . 27 Formats with 10-bitaddresses. . . . . . . . . . 27 General call address and start byte with 10-bit addressing . . . . . . . . . . . . . . . . . . . . 30 ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES . . . . . . . . . . . . . . . . . . . . 30 Standard- and Fast-mode devices. . . . . . . 30 Hs-mode devices . . . . . . . . . . . . . . . . . . . . 34 ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THEBUS LINES . 37 Maximum and minimum values of resistors Rp and Rs for Standard-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 APPLICATION INFORMATION . . . . . . . . . 41 Slope-controlled output stages of Fast-mode I2C-bus devices . . . . . . . . . . . . 41 Switched pull-up circuit for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 Wiring pattern of the buslines . . . . . . . . . . 42 Maximum and minimum values of resistors Rp and Rs for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 Maximum and minimum values of resistors Rp and Rs for Hs-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 BI-DIRECTIONAL LEVEL SHIFTER FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 Connecting devices with different logic levels . . . .. . . . . . . . . . . . . . . . . . . . . 43 Operation of the level shifter . . . . . . . . . . . 44 DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS . . . . . . . . . . . . . . . . . . . . . 45 SUPPORT LITERATURE . . . . . . . . . . . . . 46
THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS . . . . . . . . . . . . . . .4 Designer benefits . . . . . . . . . . . . . . . . . . . . 4 Manufacturer benefits. . . . . . . . . . . . . . . . . 6 INTRODUCTION TO THE SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 GENERAL CHARACTERISTICS . . . . . . . . .8 BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 START and STOP conditions . . . . . . . . . . . 9 TRANSFERRING DATA .. . . . . . . . . . . . . .10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 ARBITRATION AND CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . .11 Synchronization . . . . . . . . . . . . . . . . . . . . 11 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 Use of the clock synchronizing mechanism asa handshake . . . . . . . . . . . 13 FORMATS WITH 7-BIT ADDRESSES . . . .13 7-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 Definition of bits in the first byte . . . . . . . . General call address . . . . . . . . . . . . . . . . . START byte . . . . . . . . . . . . . . . . . . . . . . . CBUS compatibility . . . . . . . . . . . . . . . . . . 15 16 17 18 I2C-BUS
15.1 15.2 16 16.1
17...
document order number: 9398 393 40011
Philips Semiconductors
The I2C-bus specification
CONTENTS 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 8.3 9 10 10.1 10.1.1 10.1.2 10.1.3 11 12 13 13.1 13.2 13.3 PREFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Version 1.0 - 1992. . . . . . . . . . . . . . . . . . .. Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . Purchase of Philips I2C-bus components . . 3 3 3 3 13.5.1 13.5.2 13.5.3 14 14.1 14.2 14.3 15 13.4 13.5 Hs-mode devices at lower speed modes . . 24 Mixed speed modes on one serial bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 F/S-mode transfer in amixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Hs-mode transfer in a mixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing requirements for the bridge in a mixed-speed bus system . . . . . . . . . . . . . . 27 10-BIT ADDRESSING . . . . . . . . . . . . . . . . 27 Definition of bits in the first two bytes. . . . . 27 Formats with 10-bitaddresses. . . . . . . . . . 27 General call address and start byte with 10-bit addressing . . . . . . . . . . . . . . . . . . . . 30 ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES . . . . . . . . . . . . . . . . . . . . 30 Standard- and Fast-mode devices. . . . . . . 30 Hs-mode devices . . . . . . . . . . . . . . . . . . . . 34 ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THEBUS LINES . 37 Maximum and minimum values of resistors Rp and Rs for Standard-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 APPLICATION INFORMATION . . . . . . . . . 41 Slope-controlled output stages of Fast-mode I2C-bus devices . . . . . . . . . . . . 41 Switched pull-up circuit for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 Wiring pattern of the buslines . . . . . . . . . . 42 Maximum and minimum values of resistors Rp and Rs for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 Maximum and minimum values of resistors Rp and Rs for Hs-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 BI-DIRECTIONAL LEVEL SHIFTER FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 Connecting devices with different logic levels . . . .. . . . . . . . . . . . . . . . . . . . . 43 Operation of the level shifter . . . . . . . . . . . 44 DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS . . . . . . . . . . . . . . . . . . . . . 45 SUPPORT LITERATURE . . . . . . . . . . . . . 46
THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS . . . . . . . . . . . . . . .4 Designer benefits . . . . . . . . . . . . . . . . . . . . 4 Manufacturer benefits. . . . . . . . . . . . . . . . . 6 INTRODUCTION TO THE SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 GENERAL CHARACTERISTICS . . . . . . . . .8 BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 START and STOP conditions . . . . . . . . . . . 9 TRANSFERRING DATA .. . . . . . . . . . . . . .10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 ARBITRATION AND CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . .11 Synchronization . . . . . . . . . . . . . . . . . . . . 11 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 Use of the clock synchronizing mechanism asa handshake . . . . . . . . . . . 13 FORMATS WITH 7-BIT ADDRESSES . . . .13 7-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 Definition of bits in the first byte . . . . . . . . General call address . . . . . . . . . . . . . . . . . START byte . . . . . . . . . . . . . . . . . . . . . . . CBUS compatibility . . . . . . . . . . . . . . . . . . 15 16 17 18 I2C-BUS
15.1 15.2 16 16.1
17...
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