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DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-freetriggering for inputs as slow as 1 volt / second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of anyduration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independentof VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 70 kΩ for the SN54LS221, and 2.0 to 100 kΩ for the SN74LS221).Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kΩ . If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.

SN54/74LS221

DUAL MONOSTABLE MULTIVIBRATORS WITHSCHMITT-TRIGGER INPUTS
LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09
16 1

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

• SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN54 / 74LS123

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

(TOP VIEW)
VCC 16 1 Rext/1 Cext Cext 15 14 Q Q CLR 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 VCC CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext Cext Rext + R/C L X X H H
*°

FUNCTION TABLE (EACH MONOSTABLE)
INPUTS CLEAR A X H X L ± L B X X L ° H H MAXIMUM OUTPUT PULSE LENGTH 49 s 70 s OUTPUTS Q L L L Q H H H

1 1A

2 1B

3 1 CLR

*See operational notes — Pulse Trigger Modes

TYPE SN54LS221 SN74LS221

positivelogic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs.

TYPICAL POWER DISSIPATION 23 mW 23 mW

FAST AND LS TTL DATA 5-1

SN54/74LS221
OPERATIONAL NOTES Once in the pulse trigger mode, the output pulse width is determined by tW = RextCextIn2, as long as Rext and Cext are within their minimum and maximum valves and the dutycycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than ±0.5% from device to device. If the duty cycle, defined as being 100 • tW where T is the T input period of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causesthe output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible. (Jitter is independent of Cext). With Rext = 100K, jitter is not appreciable until the duty cycle approaches 90%. Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that...