Informatica

Addressing Modes
Table 3-2. Summary of Indexed Operations
Postbyte Code (xb) Source Code Syntax ,r n,r –n,r Comments rr; 00 = X, 01 = Y, 10 = SP, 11 = PC 5-bitconstant offset n = –16 to +15 r can specify X, Y, SP, or PC Constant offset (9- or 16-bit signed) z- 0 = 9-bit with sign in LSB of postbyte(s) 1 = 16-bit if z = s = 1,16-bit offset indexed-indirect (see below) r can specify X, Y, SP, or PC 16-bit offset indexed-indirect rr can specify X, Y, SP, or PC

rr0nnnnn

111rr0zs

n,r–n,r

–256 � n � 255 –32,768 � n � 65,535

111rr011

[n,r]

–32,768 � n � 65,535

rr1pnnnn

n,–r n,+r n,r– n,r+

Auto predecrement, preincrement,postdecrement, or postincrement; p = pre-(0) or post-(1), n = –8 to –1, +1 to +8 r can specify X, Y, or SP (PC not a valid choice) +8 = 0111 … +1 = 0000 –1 = 1111 … –8 = 1000Accumulator offset (unsigned 8-bit or 16-bit) aa-00 = A 01 = B 10 = D (16-bit) 11 = see accumulator D offset indexed-indirect r can specify X, Y, SP, or PC Accumulator Doffset indexed-indirect r can specify X, Y, SP, or PC

111rr1aa

A,r B,r D,r

111rr111

[D,r]

Indexed addressing mode instructions use a postbyte to specifyindex registers (X and Y), stack pointer (SP), or program counter (PC) as the base index register and to further classify the way the effective address is formed. Aspecial group of instructions cause this calculated effective address to be loaded into an index register for further calculations: � � �
Reference Manual 40 AddressingModes

Load stack pointer with effective address (LEAS) Load X with effective address (LEAX) Load Y with effective address (LEAY)
CPU12 — Rev. 5.0 MOTOROLA