Integrados

Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
Datasheet

January 2003

Order Number: 252337-001

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intelassumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustainingapplications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® I/OController Hub 4 Mobile (ICH4-M) chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communicationsbus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Copies of documents which have an orderingnumber and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.Copyright © 2002, Intel Corporation

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Intel® 82801DBM ICH4-M Datasheet

Intel® 82801DBM ICH4 Features
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— Supports PCI Revision 2.2 Specification at 33 MHz — 133 MB/sec maximum throughput — Supports up to 6 master devices on PCI — One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) —Support for 44-bit addressing on PCI using DAC protocol Integrated LAN Controller — WfM 2.0 and IEEE 802.3 compliant — LAN Connect Interface (LCI) — 10/100 Mbit/sec ethernet support Integrated IDE Controller — Supports “Native Mode” register and interrupts — Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections — Ultra ATA/100/66/33, BMIDE and PIO modes —Tri-state modes to enable swap bay USB — Includes 3 UHCI host controllers that support 6 external ports — New: Includes 1 EHCI high-speed USB 2.0 Host Controller that supports all six ports — New: Supports a USB 2.0 high-speed debug port — Supports wake-up from sleeping states S1-M–S5 — Supports legacy keyboard/mouse software AC'97 Link for Audio and Telephony CODECs — New: Third AC_SDATA_IN linefor three codec support — Supports AC ’97 2.3 — New: Independent bus master logic for 7 channels (PCM In/Out, Mic 1 input, Mic 2 input, modem in/out, S/PDIF out) — Separate independent PCI functions for audio and modem — Support for up to six channels of PCM audio output (full AC3 decode) — Supports wake-up events Interrupt Controller — Support up to 8 PCI interrupt pins — Supports PCI 2.2...