Ir2112

Data Sheet No. PD60026 revS

IR2112(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features

• Floating channel designed for bootstrap operation
• Fully operational to +600V
• Tolerant to negative transient voltage
dV/dt immune

• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible
•
•
•
•

Separate logic supply range from 3.3V to 20VLogic and power ground ±5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs

Product Summary
VOFFSET

600V max.

IO+/-

200 mA / 420 mA

VOUT

10 - 20V

ton/off (typ.)

125 & 105 ns

Delay Matching

30 ns

Packages

Description
The IR2112(S) is ahigh voltage, high speed power
MOSFET and IGBT driver with independent high and
16-Lead SOIC (wide body)
low side referenced output channels. Proprietary HVIC
14-Lead PDIP
and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic.
The output drivers feature a high pulse current buffer stagedesigned for minimum driver cross-conduction.
Propagation delays are matched to simplify use in high frequency applications. The floating channel can be
used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600
volts.

Typical Connection

up to 600V

HO
VDD

VDD

VB

HIN

HIN

VS

SD

SD

LIN

LIN

VCC

VSS

VSS

COMVCC

TO
LOAD

LO

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.

www.irf.com

1

IR2112(-1-2)(S)PbF

Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur.All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol

Definition

VB
VS

Min.

Max.

-0.3

High Side Floating Supply Voltage

625

Units

High Side Floating Supply Offset Voltage

V B - 25VB + 0.3

VHO

High Side Floating Output Voltage

VS - 0.3

VB + 0.3

VCC

Low Side Fixed Supply Voltage

-0.3

25

VLO

Low Side Output Voltage

-0.3

VCC + 0.3

VDD

Logic Supply Voltage

-0.3

VSS + 25

VSS

Logic Supply Offset Voltage

VCC - 25

VCC + 0.3

VIN

Logic Input Voltage (HIN, LIN & SD)

dVs/dt
PD

VSS - 0.3

VDD + 0.3Allowable Offset Supply Voltage Transient (Figure 2)

—

50

Package Power Dissipation @ TA ≤ +25°C

—

1.25

(14 Lead DIP)

—

75

—

V/ns

1.6

—

(16 Lead SOIC)

Thermal Resistance, Junction to Ambient

(14 Lead DIP)
(16 Lead SOIC)

RTHJA

V

100

TJ

Junction Temperature

—

Storage Temperature

-55

150

TL

Lead Temperature (Soldering, 10seconds)

—

°C/W

150

TS

W

300

°C

Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in Figures 36 and 37.

SymbolMin.

Max.

VB

High Side Floating Supply Absolute Voltage

Definition

VS + 10

VS + 20

VS

High Side Floating Supply Offset Voltage

Note 1

600
VB

VHO

High Side Floating Output Voltage

VS

VCC

Low Side Fixed Supply Voltage

10

20

VLO

Low Side Output Voltage

0

VCC

VDD

Logic Supply Voltage

VSS

Logic Supply Offset Voltage

VIN...