Jonathan

74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 8 — 19 July 2012 Product data sheet

1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enableinput (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs(S0 to S2, and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

2. Features and benefits
 Wide analoginput voltage range from 5 V to +5 V  Low ON resistance:  80  (typical) at VCC  VEE = 4.5 V  70  (typical) at VCC  VEE = 6.0 V  60  (typical) at VCC  VEE = 9.0 V  Logic level translation: to enable 5 V logic to communicate with 5 V analog signals  Typical ‘break before make’ built-in  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDMJESD22-C101E exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C

NXP Semiconductors

74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer

3. Applications
 Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating

4. Ordering information
Table 1. Ordering information Package Temperature range74HC4053N 74HCT4053N 74HC4053D 74HCT4053D 74HC4053DB 74HCT4053DB 74HC4053PW 74HCT4053PW 74HC4053BQ 74HCT4053BQ 40 C to +125 C 40 C to +125 C TSSOP16 40 C to +125 C SSOP16 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mmSOT109-1 SOT338-1 SOT403-1 SOT763-1 40 C to +125 C Name DIP16 Description plastic dual in-line package; 16 leads (300 mil) Version SOT38-4 Type number

DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm

74HC_HCT4053

All information provided in this document is subject to legal disclaimers.

© NXP B.V.2012. All rights reserved.

Product data sheet

Rev. 8 — 19 July 2012

2 of 32

NXP Semiconductors

74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer

5. Functional diagram
E 6 VCC 16

13 1Y1

S1 11

LOGIC LEVEL CONVERSION

DECODER

12 1Y0

14 1Z

1 2Y1

S2 10

LOGIC LEVEL CONVERSION

2 2Y0

15 2Z

3 3Y1

S3 9

LOGIC LEVEL CONVERSION5 3Y0

4 3Z

8 GND

7 VEE

001aak341

Fig 1.

Functional diagram

6 11 10 9 S1 S2 S3 1Y0 1Y1 1Z 2Y0 2Y1 2Z 3Y0 3Y1 6 E 3Z 12 13 14 2 1 15 5 3 4
10 15 # 11 14 #

EN

×

MUX/DMUX 0 0 1 1

12 13

0/1

2 1

9 4

#

5 3
001aae126

001aae125

Fig 2.
74HC_HCT4053

Logic symbol

Fig 3.

IEC logic symbol
© NXP B.V. 2012. All rights reserved.

Allinformation provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 July 2012

3 of 32

NXP Semiconductors

74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer

Y VCC VEE

VCC

VCC

VCC from logic VEE Z

VEE

001aad544

Fig 4.

Schematic diagram (one switch)

6. Pinning information
6.1 Pinning

74HC4053 74HCT4053
2Y1...