Led Rgb

HL1606
DESCRIPTION
HL1606 is a LED driver IC with SPI controlled. We can get “complex mode changes” by fewer data.

FEATURES
NMOS output SPI controlled，plus synchronization speed control port: S-I PWM output,frequency:500Hz With a internal “change model” unit，only data calls, reducing the amount of data. Speed control bit，can speed up “changes in a pixel” rate of 2 times. Latch enablebit，concatenated string at a point can be read or not read data. Built-6 road, drive two pixels（three-output get a pixel）

Pin definition

No. 1 2 3 4 5 6

Name S-I D-I CK-I L-I L-O CK-O

Description Sync / speed clock input Data input Clock input Latch signal input Latch signal buffer output Clock buffer output

No. 7 8 9 10~12 13~15 16

Name D-O S-O GND B3~B1 A3~A1 VDD

Description Databuffer output Sync / speed clock buffer output GND 3 way drive output 3 way drive output VDD

Data format
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 HIGH

A1~A3 LED Control data-1

B1~B3 LED Control date-2

Data format of A1-A3 LED Control data-1(B1-B3 LED Control data-2 can refer it) D1（D9） D2（D10） D3（D11） D4（D12） A2（B2）Control bit D5（D13） D6（D14） A3（B3）Control bit D7（D15）D8（D16） Control bit of speed Latch enable bit

A1（B1）Control bit

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D2=0、D1=0 A1 Light out D2=0、 D1=1 A1 Light on D2=1、D1=0 A1 fadein D2=1、D1=1 A1 fadeout

D4=0、 D3=0 A2 Light out D4=0、D3=1 A2 Light on D4=1、D3=0 A2 fadein D4=1、D3=1 A2 fadeout

D6=0、D5=0 A3 Light out D6=0、 D5=1 A3 Light on D6=1、D5=0 A3 fadein D6=1、 D5=1 A3 fadeout

D7=0 Default rate D7=1 2 times rate

D8=0 Cannot latch D8=1 Allowed to latch

Description of build-in module
Fadein module： When a data bit is 10(D2D1 or D4D3 or D6D5) and the latch is enable, corresponding output state of LED is fadein. After get the brightest state, it will keep the state, until the new data input by effective latch. Fadeout module： When a data bit is 11(D2D1 or D4D3 or D6D5) and the latch is enable, corresponding outputstate of LED is fadeout. After the lights out, it will keep the state, until the new data input by effective latch. Cycle time of change--T： T When D7=0,T=Tzc×128 set ,series is 128. For example: When Zc=50Hz,T=2.56s,if every latch is effective, fadein/fadeout module will resume the change.

Electric parameter （VDD=5V，temperature=25℃）
ITEM Threshold voltage of output tube Operating voltageOperating current DATA input, changes of high level and low level Output current of drive Output current of buffer temperature Work frequency of terminal-S SYMBOL VOL VCC ICC VIN IOL IOH IOL Temp Fs VDD=5V TEST CONDITIONS IDS≤1µA，VDD=5V Stable and functioning properly VDD=5V，oscillations, no load Stable and functioning properly VDD=5V，VDS=0.8V VDD=5V，VDS=-0.8V VDD=5V，VDS=0.8V MIN. -3 -3.8 ---0 TYP. -5200 -30 5 10 25 MAX. 6 5.5 400 6 ---70 200 UNIT V V µA V mA mA mA ℃ Hz

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Timing diagram(entry data from high level)
t0≥300ns ；t1≥1µs；T≥250N(ns)，N: the number of cascade；t2≈100ns。

Impression Drawing & Data Format 1. Monochrome , one-way, gradually run

Running direction

Description: There is a “gradual change” mode in HL1606, so D_I only need one set of data”10110000”,then input ”0” to the end is okay. Clock signal has been sent to CK_I, sent a “1” to L_I after 8 clock signal. Change once the signal of S_I, the output decline in a series. A clock cycle in S_I,. output is keep in 512Hz refresh frequency, to maintain the same level(series) of output duty cycle refresh. If no data sent to S_I,
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output will remain the same duty cycle refresh.

2.Colorful fluttering

Fluttering direction

Description: There is a “gradual change” mode in HL1606, so D_I only need one set of data”10001011”, then input ”0” to the end is okay(red to green gradually). Clock signal has been sent to CK_I, sent a “1” to L_I after 8 clock signal. Change once the signal of S_I, the output series change once. A clock cycle in S_I,. output is keep in 512Hz...