Memorias
CSEE W4840
Prof. Stephen A. Edwards Columbia University
Memory – p. 1/
Early Memories
Williams Tube CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits.Memory – p. 2/
Early Memories
Mercury acoustic delay line. Used in the EDASC, 1947. 32 × 17 bits
Memory – p. 3/
Early Memories
Magnetic core memory, 1952. IBM.
Memory – p. 4/Early Memories
Magnetic drum memory. 1950s & 60s. Secondary storage.
Memory – p. 5/
Modern Memory Choices
Family Programmed Persistence
∞ ∞
Mask ROM at fabrication PROM EPROM FLASHEEPROM NVRAM SRAM DRAM once 1000s, UV 1000s, block 1000s, byte
∞ ∞ ∞
10 years 10 years 10 years 5 years while powered 64 ms
Memory – p. 6/
ROMs
Memory – p. 7/
EPROMs
Memory – p. 8/EEPROM and FLASH
Slow write Oxide FowlerNordheim Tunneling EEPROM: bit at a time FLASH: block at a time
Source: SST
floating gate Word Line Drain Channel (bit line)
Source
Memory – p. 9/Static RAM Cell
Word
Bit
Bit
Memory – p. 10/
Standard SRAM: 6264
19–15,13–11 D[7:0] 10–2,25–23,21 22 27 20 26
Addr[12:0] OE WE CS1 CS2
8K × 8 Can be very fast: Cypress sellsa 55ns version Simple, asynchronous interface
Memory – p. 11/
OE
WE
CS2
CS1
Addr
Standard SRAM: 6264
Data
¢ ¡ ¢ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¢ ¡ ¢ ¢ ¢ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¢ ¡ ¢ ¡ ¢ ¡
Memory – p. 12/
provided by an active LOW chip enable (CE1), an active HIGHchip enable (CE2), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic power-down feature (CE1), reducing the power consumption by
Standard SRAM: 6264
LogicBlock Diagram
The input/output pins remain in a hi the chip is selected, outputs are (WE) is HIGH. A die coat is used to
Pin C
I/O0 INPUT BUFFER I/O1 A1 A2 A3 A4 A5 A6 A7 A8 I/O2 I/O3 256 x...
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