Microcontroladores

PIC18F26K20/46K20
PIC18F26K20/46K20 Rev. A4 Through A5 Silicon/Data Sheet Errata
The PIC18F26K20/46K20 parts you have received
conform functionally to the Device Data Sheet
(DS41303C) and the Programming Specification
(DS41297D), except for the anomalies described
below.
All problems listed here will be addressed in future
revisions of the PIC18F26K20/46K20 silicon.

1. Module: ECCPChanging the CCP1M bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.

2. Module: ECCP
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of thebridge.
Work around
None.

3. Module: MSSP I2C™
Slew rate is slower than I2C specifications when
the SLRCON bit is set.

5. Module: MSSP I2C
If a new address byte is received while the BF flag
is set, the SSPOV bit is set and an ACK is not
generated, both of which are proper operation. If
only the SSPOV bit is set (BF flag was cleared)
and a matching address is clocked in, that
receivedbyte will be loaded into the SSPBUF
register and an ACK will be generated, both of
which are improper operation.
Work around
None.

6. Module: MSSP I2C
In Master I2C mode, when a slave device releases
the clock after holding it low (clock stretching), the
pulse width of the first high clock cycle may be
shorter than half the clock period.
Work around
None.

7. Module: MSSP I2C
InMaster I2C mode, baud rates obtained by
setting SSPADD to a value less than 0x03 will
cause unexpected operation.
Work around
Ensure SSPADD is set to a value greater than or
equal to 0x04.

Work around
Clear SLRCON bit when using the I2C
peripheral.

4. Module: ADC

8. Module: MSSP SPI
When the SPI clock is configured for Timer2 output/2
(SSPCON1 = 0011), the first SPI high time
may beshort.

Offset error is 3 LSb typical, 7 LSb maximum,
including an acquisition time dependent
component (~2 LSb).

Work around

Work around

Option 2: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after SSPBUF is
written.

The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversionis
greater than 100 ms then take two ADC
conversions and discard the first.

© 2008 Microchip Technology Inc.

Option 1: Ensure TMR2 value rolls over to zero
immediately before writing to SSPBUF.

DS80379A-page 1

PIC18F26K20/46K20
9. Module: MSSP SPI
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDIpin will not be
sampled properly.
Work around
None.

10. Module: MSSP SPI
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift register
on every high-to-low transition of the SS pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.

11. Module: MSSP SPI
When SPI is enabled in Master mode withCKE = 1 and CKP = 0, a 1/FOSC wide pulse will
occur on the SCK pin.
Work around
Configure the SCK pin as an input until after the
MSSP is setup.

12. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.

13.Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register, the
LS bit of the TXREG character may be corrupted
during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted....