Microprosesador Z80

Z80 Family
CPU User Manual
User Manual
UM008005-0205

ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com

Z80 CPU
User’s Manual

This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG WorldwideHeadquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com

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and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2004 by ZiLOG, Inc. All rights reserved.Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
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UM008005-0205

Z80 CPU
User’s Manualiii

Revision History
Each instance in Table 1 reflects a change to this document from
its previous revision. To see more detail, click the appropriate link
in the table.
Table 1. Revision History of this Document

Date

Revision
Level
Section

Description

December 04
2004

Z80 Instruction Corrected discrepancies in the bit
Set
patterns for IM 0, IM 1 and IM 2
instructions.February
2005

Z80 Instruction
Set, CPU
Instruction
Description

Page #

05

Chapter Title

176,177,
178

Corrected illustration for the Rotate and
Shift Group RLCA instruction. Also
corrected the hex code for the RLCA
instruction on page 63.

190, 63

UM008005-0205

Z80 CPU
User’s Manual
iv

UM008005-0205

PRELIMINARY DRAFT v1.0

Chapter Title

Z80 CPUUser’s Manual

v

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
CPU Registers . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 2
Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Instruction Register and CPU Control . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .12
Memory Read Or Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Input or Output Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . .15
Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . .16
Non-Maskable Interrupt Response . . . ....