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CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003

D D D D D

2-V to 6-V VCC Operation Wide Operating Temperature Range of –55°C to 125°C Balanced Propagation Delays and Transition Times Standard Outputs Drive up to 15 LS-TTL Loads Significant Power Reduction Compared to LS-TTL Logic ICs

CD54HC373 . . . F PACKAGECD74HC373 . . . E OR M PACKAGE (TOP VIEW)

description/ordering information
The ’HC373 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation.

OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE

When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, theQ outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines withoutinterface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of thedriver. ORDERING INFORMATION
TA PACKAGE† PDIP – E –55°C to 125°C 55°C SOIC – M CDIP – F Tube Tube Tape and reel Tube ORDERABLE PART NUMBER CD74HC373E CD74HC373M CD74HC373M96 CD54HC373F3A TOP-SIDE MARKING CD74HC373E HC373M CD54HC373F3A

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be awarethat an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing doesnot necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

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CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003

FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z

logic diagram (positive logic)
OE 1

LE

11 C1 2

1D

3

1D

1Q

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous outputdrain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package...