Procesador mips

MIPS/SPIM Reference Card
CORE INSTRUCTION SET (INCLUDING PSEUDO INSTRUCTIONS)
MNE- FORMON- MAT NAME IC Add add R Add Immediate addi I Add Imm. Unsigned addiuI Add Unsigned addu R Subtract sub R Subtract Unsigned subu R And and R And Immediate andi I Nor nor R Or or R Or Immediate ori I Xor xor R Xor Immediate xori IShift Left Logical sll R Shift Right Logical srl R Shift Right Arithmetic sra R Shift Left Logical Var. sllv R Shift Right Logical Var. srlv R Shift RightArithmetic Var. srav R Set Less Than slt R Set Less Than Imm. slti I Set Less Than Imm. Unsign. sltiu I Set Less Than Unsigned sltu R Branch On Equal beq I Branch OnNot Equal bne I Branch Less Than blt P Branch Greater Than bgt P Branch Less Than Or Equal ble P Branch Greater Than Or Equal bge P Jump j J Jump And Link jal JJump Register Jump And Link Register Move Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Upper Imm. Load Word Load Immediate Load AddressStore Byte Store Halfword Store Word jr jalr move lb lbu lh lhu lui lw li la sb sh sw R R P I I I I I I P P I I I OPCODE/ FUNCT (Hex) 0/20 8 9 0/21 0/22 0/230/24 c 0/27 0/25 d 0/26 e 0/00 0/02 0/03 0/04 0/06 0/07 0/2a a b 0/2b 4 5

OPERATION (in Verilog) R[rd]=R[rs]+R[rt] R[rt]=R[rs]+SignExtImm R[rt]=R[rs]+SignExtImmR[rd]=R[rs]+R[rt] R[rd]=R[rs]-R[rt] R[rd]=R[rs]-R[rt] R[rd]=R[rs]&R[rt] R[rt]=R[rs]&ZeroExtImm R[rd]=∼(R[rs]|R[rt]) R[rd]=R[rs]|R[rt] R[rt]=R[rs]|ZeroExtImmR[rd]=R[rs]ˆR[rt] R[rt]=R[rs]ˆZeroExtImm R[rd]=R[rs] shamt R[rd]=R[rs] shamt R[rd]=R[rs] >shamt R[rd]=R[rs] R[rt] R[rd]=R[rs] R[rt] R[rd]=R[rs] >R[rt] R[rd]=(R[rs]