Programacion

MC14504B Hex Level Shifter for TTL to CMOS or CMOS to CMOS
The MC14504B is a hex non−inverting level shifter using CMOS technology. The level shifter will shift a TTL signal to CMOS logic levels for any CMOS supply voltage between 5 and 15 volts. A control input also allows interface from CMOS to CMOS at one logic level to another logic level: Either up or down level translating is accomplishedby selection of power supply levels VDD and VCC. The VCC level sets the input signal levels while VDD selects the output voltage levels.
Features http://onsemi.com MARKING DIAGRAMS
PDIP−16 P SUFFIX CASE 648 16 MC14504BCP AWLYYWW 1

• UP Translates from a Low to a High Voltage or DOWN Translates • • • • • •
from a High to a Low Voltage Input Threshold Can Be Shifted for TTL Compatibility NoSequencing Required on Power Supplies or Inputs for Power Up or Power Down 3 to 18 Vdc Operation for VDD and VCC Diode Protected Inputs to VSS Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range Pb−Free Packages are Available*
Parameter DC Supply Voltage Range DC Supply Voltage Range Input Voltage Range (DC or Transient) Output VoltageRange (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8−Second Soldering) Value −0.5 to +18.0 −0.5 to +18.0 −0.5 to +18.0 −0.5 to VDD + 0.5 ± 10 500 −55 to +125 −65 to +150 260 Unit V V V V mA mW °C °C °C

16 SOIC−16 D SUFFIX CASE 751B 1 14504B AWLYWW

16 TSSOP−16 DTSUFFIX CASE 948F 1 14 504B ALYW

MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VCC VDD Vin Vout Iin, Iout PD TA Tstg TL

16 SOEIAJ−16 F SUFFIX CASE 966 1 MC14504B AWLYWW

A WL, L YY, Y WW, W

= Assembly Location = Wafer Lot = Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_CFrom 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always betied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2005

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

1

February, 2005 − Rev. 5

Publication Order Number:MC14504B/D

MC14504B
PIN ASSIGNMENT
VCC Aout Ain Bout Bin Cout Cin VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Fout Fin MODE Eout Ein Dout Din MODE TTL/CMOS MODE SELECT INPUT LEVEL SHIFTER OUTPUT VCC VDD

LOGIC DIAGRAM

Mode Select 1 (VCC) 0 (VSS) 1/6 of package shown.

Input Logic Levels TTL CMOS

Output Logic Levels CMOS CMOS

ORDERING INFORMATION
Device MC14504BCP MC14504BCPGMC14504BD MC14504BDG MC14504BDR2 MC14504BDR2G MC14504BDT MC14504BDTR2 MC14504BF MC14504BFEL Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* SOEIAJ−16 SOEIAJ−16 Shipping† 500 Units / Rail 500 Units / Rail 48 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail 2000...