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Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
Logic Device – 64 Macrocells – 5.0 ns Pin-to-pin Propagation Delay – Registered Operation up to 333 MHz – Enhanced Routing Resources – Optimized for 1.8V Operation – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V – SSTL2 and SSTL3 I/O Standards In-System Programming (ISP) Supported– ISP Using IEEE 1532 (JTAG) Interface – IEEE 1149.1 JTAG Boundary Scan Test Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops – 5 Product Terms per Macrocell, Expandable up to 40 – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate with Low Output Drive – Programmable Open Collector Output Option – Maximum LogicUtilization by Burying a Register with a Combinatorial Output and Vice Versa Fully Green (RoHS Compliant) 10 µA Standby Current Power Saving Option During Operation Using PD1 and PD2 Pins Programmable Pin-keeper Option on Inputs and I/Os Programmable Schmitt Trigger Option on Input and I/O Pins Programmable Input and I/O Pull-up Option Unused I/O Pins Can Be Configured as Ground (Optional) Available inCommercial and Industrial Temperature Ranges Available in 44-lead and 100-lead TQFP Advanced Digital CMOS Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity Security Fuse Feature Hot-Socketing Supported





Highperformance CPLD ATF1504BE

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3637B–PLD–1/08 Enhanced Features
• • • • • • • • •
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms Outputs Can Be Configured for High or Low Drive Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell Three Global Clock Pins Fast Registered Input from Product Term Pull-up Option on TMS and TDI JTAG Pins OTF (On-the-Fly)Reconfiguration Mode DRA (Direct Reconfiguration Access)

1. Description
The ATF1504BE is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504BE’s enhanced routing switchmatrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504BE has up to 64 bi-directional I/O pins and four dedicated input pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Figures 1-1 and1-2 show the pin assignments for the 100-lead and 44-lead TQFP packages respectively.

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ATF1504BE
3637B–PLD–1/08

ATF1504BE
Figure 1-1. 100-lead TQFP Top View
I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIOB I/O I/O I/O NC NC I/O

NC NC VCCIOA I/O/TDI NC I/O NC I/O I/O I/O GND VREFA/I/O/PD1 I/O I/O I/O/TMS I/O I/OVCCIOA I/O I/O I/O NC I/O NC I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIOB I/O I/O I/OI/O/TCK I/O I/O/VREFB GND I/O I/O I/O NC I/O NC I/O VCCIOB

GND NC NC I/O I/O I/O I/O I/O VCCIOA I/O I/O I/O GND VCCINT I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O NC NC

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3637B–PLD–1/08

Figure 1-2.

44-lead TQFP Top View
I/O I/O I/O VCCINT GCLK2/OE2/I GCLR/I I/OE1 GCLK1/I GND GCLK3/I/O I/O 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22...
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