Spartan
Páginas: 80 (19826 palabras)
Publicado: 3 de junio de 2010
0
R
Spartan-3A FPGA Family: Data Sheet
0 0
DS529 May 28, 2008
Product Specification
Bitstream Sizes Detailed Descriptions by Mode · Master Serial Mode using Platform Flash PROM · Master SPI Mode using Commodity Serial Flash · Master BPI Mode using Commodity Parallel Flash · Slave Parallel (SelectMAP) using a Processor · Slave Serial using a Processor · JTAG Mode ISE iMPACTProgramming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
Module 1: Introduction and Ordering Information
DS529-1 (v1.7) May 28, 2008
• • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities Production Status Supported Packages and Package Marking Ordering Information
•Module 2: Functional Description
DS529-2 (v1.7) May 28, 2008 The functionality of the Spartan®-3A FPGA family is described in the following documents.
• UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) · Distributed RAM · SRL16 Shift Registers · Carry and Arithmetic Logic I/O Resources Embedded Multiplier BlocksProgrammable Interconnect ISE® Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior
Module 3: DC and Switching Characteristics
DS529-3 (v1.7) May 28, 2008
• DC Electrical CharacteristicsAbsolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions Switching Characteristics I/O Timing Configurable Logic Block (CLB) Timing Multiplier Timing Block RAM Timing Digital Clock Manager (DCM) Timing Suspend Mode Timing Device DNA Timing Configuration and JTAG Timing
•
Module 4: Pinout Descriptions
DS529-4 (v1.7) May 28, 2008
• • • • Pin Descriptions PackageOverview Pinout Tables Footprint Diagrams
•
Spartan-3A FPGA XC3S50A XC3S200A XC3S400A XC3S700A XC3S1400A
Status PRODUCTION PRODUCTION PRODUCTION PRODUCTION PRODUCTION
www.xilinx.com/spartan3a
© 2006-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PCI is a registered trademark ofthe PCI-SIG. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS529 May 28, 2008 Product Specification
www.xilinx.com
1
Spartan-3A FPGA Family: Data Sheet
R
2
www.xilinx.com
DS529 May 28, 2008 Product Specification
R
< B L B
Spartan-3A FPGA Family: Introduction and Ordering InformationProduct Specification
DS529-1 (v1.7) May 28, 2008
Introduction
The Spartan®-3A family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, I/O-intensive electronic applications. The five-member family offers densities ranging from 50,000 to 1.4 million system gates, as shown in Table 1. The Spartan-3A family builds on the success of theearlier Spartan-3E and Spartan-3 FPGA families by increasing the amount of I/O per logic, significantly reducing the cost per I/O. New features improve system performance and reduce the cost of configuration. These Spartan-3A family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in theprogrammable logic industry. Because of their exceptionally low cost, Spartan-3A FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3A family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the...
R
Spartan-3A FPGA Family: Data Sheet
0 0
DS529 May 28, 2008
Product Specification
Bitstream Sizes Detailed Descriptions by Mode · Master Serial Mode using Platform Flash PROM · Master SPI Mode using Commodity Serial Flash · Master BPI Mode using Commodity Parallel Flash · Slave Parallel (SelectMAP) using a Processor · Slave Serial using a Processor · JTAG Mode ISE iMPACTProgramming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
Module 1: Introduction and Ordering Information
DS529-1 (v1.7) May 28, 2008
• • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities Production Status Supported Packages and Package Marking Ordering Information
•Module 2: Functional Description
DS529-2 (v1.7) May 28, 2008 The functionality of the Spartan®-3A FPGA family is described in the following documents.
• UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) · Distributed RAM · SRL16 Shift Registers · Carry and Arithmetic Logic I/O Resources Embedded Multiplier BlocksProgrammable Interconnect ISE® Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior
Module 3: DC and Switching Characteristics
DS529-3 (v1.7) May 28, 2008
• DC Electrical CharacteristicsAbsolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions Switching Characteristics I/O Timing Configurable Logic Block (CLB) Timing Multiplier Timing Block RAM Timing Digital Clock Manager (DCM) Timing Suspend Mode Timing Device DNA Timing Configuration and JTAG Timing
•
Module 4: Pinout Descriptions
DS529-4 (v1.7) May 28, 2008
• • • • Pin Descriptions PackageOverview Pinout Tables Footprint Diagrams
•
Spartan-3A FPGA XC3S50A XC3S200A XC3S400A XC3S700A XC3S1400A
Status PRODUCTION PRODUCTION PRODUCTION PRODUCTION PRODUCTION
www.xilinx.com/spartan3a
© 2006-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PCI is a registered trademark ofthe PCI-SIG. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS529 May 28, 2008 Product Specification
www.xilinx.com
1
Spartan-3A FPGA Family: Data Sheet
R
2
www.xilinx.com
DS529 May 28, 2008 Product Specification
R
< B L B
Spartan-3A FPGA Family: Introduction and Ordering InformationProduct Specification
DS529-1 (v1.7) May 28, 2008
Introduction
The Spartan®-3A family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, I/O-intensive electronic applications. The five-member family offers densities ranging from 50,000 to 1.4 million system gates, as shown in Table 1. The Spartan-3A family builds on the success of theearlier Spartan-3E and Spartan-3 FPGA families by increasing the amount of I/O per logic, significantly reducing the cost per I/O. New features improve system performance and reduce the cost of configuration. These Spartan-3A family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in theprogrammable logic industry. Because of their exceptionally low cost, Spartan-3A FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3A family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the...
Leer documento completo
Regístrate para leer el documento completo.