Tareas

AT28C64/X
Features

• • • • • • • • • •

Fast Read Access Time - 120 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor Control READY/BUSY Open Drain Output DATA Polling Low Power 30 mA Active Current 100 µA CMOS Standby Current High Reliability Endurance: 104 or 105Cycles Data Retention: 10 Years 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Commercial and Industrial Temperature Ranges

64K (8K x 8) CMOS E2PROM

Description
The AT28C64 is a low-power, high-performance 8,192 words by 8 bit nonvolatile Electrically Erasable and Programmable Read Only Memory with popular, easy to use features. The device ismanufactured with Atmel’s reliable nonvolatile technology. (continued)

Pin Configurations
Pin Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/BUSY NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don’t Connect

PDIP, SOIC Top View AT28C64/X

LCC, PLCC Top View TSOP Top View

Note: PLCC package pins 1 and 17 are DON’T CONNECT.

0001G2-193

Description (Continued)
The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write thelatched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected thestandby current is less than 100 µA. Atmel’s 28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32-bytes of E2PROM are available for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*
Temperature UnderBias................. -55°C to +125°C Storage Temperature...................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute MaximumRatings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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AT28C64/X

AT28C64/X
Device Operation
READ:The AT28C64 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the AT28C64 is similar towriting into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the falling edge of WE (or CE); the new data is latched on the rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a...