Tareas

M25PXX
512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface
DATA BRIEF

FEATURES SUMMARY
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512Kbit to 32Mbit of Flash Memory Page Program (up to 256 Bytes) in 1.4ms (typical) Sector Erase (256 Kbit or 512Kbit) Bulk Erase (512Kbit to 32Mbit) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 40MHz to 50MHzClock Rate (maximum) Deep Power-down Mode 1µA (typical) Electronic Signatures – JEDEC Standard Two-Byte Signature (20xxh) – RES Instruction, One-Byte, Signature, for backward compatibility More than 100000 Erase/Program Cycles per Sector More than 20 Year Data Retention

Figure 1. Packages

VDFPN8 (ME) 8x6mm (MLP8)

VDFPN8 (MP) (MLP8)

Table 1. Product List
Reference Part Number M25P32M25P16 M25P80 M25Pxx M25P40 M25P20 M25P10-A M25P05-A SO16 (MF) 300 mil width

8 1
SO8 (MN) 150 mil width

October 2004
For further information contact your local ST sales office.

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SUMMARY DESCRIPTION
The M25Pxx is a 512Kbit to 32Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can beprogrammed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as a number of sectors, each containing 256 or 128 pages. Each page is 256 bytes wide. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram
VCC

Figure 3. SO8 and VDFPN Connections

M25Pxx S Q W VSS 1 2 3 4 87 6 5
AI10259

VCC HOLD C D

D C S W HOLD M25Pxx

Q

Note: 1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V SS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

Figure 4. SO16 Connections
M25Pxx HOLD VCC DU DU DU DU S Q 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
AI10260

VSS
AI10258

Table2. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground

C D DU DU DU DU VSS W

Note: 1. DU = Don’t Use

S
W HOLD VCC VSS

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Figure 5. Block Diagram

HOLD W S C D Q Control Logic

High Voltage Generator

I/O Shift Register

Address Register and Counter

256 Byte Data Buffer

Status RegisterTop of Address Space

Y Decoder

Size of the read-only memory area

00000h 256 Bytes (Page Size) X Decoder

000FFh

AI10261

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Table 3. Instruction Set
Instruction WREN WRDI RDID RDSR WRSR READ Description Write Enable Write Disable Read Identification Read Status Register Write Status Register Read Data Bytes One-byte Instruction Code 0000 0110 0000 0100 1001 1111 00000101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 06h 04h 9Fh 05h 01h 03h 0Bh 02h D8h C7h B9h Address Bytes 0 0 0 0 0 3 3 3 3 0 0 0 1010 1011 ABh 0 0 Dummy Bytes 0 0 0 0 0 0 1 0 0 0 0 3 Data Bytes 0 0 1 to 3 1 to ∞ 1 1 to ∞ 1 to ∞ 1 to 256 0 0 0 1 to ∞ 0

FAST_READ Read Data Bytes at Higher Speed PP SE BE DP Page Program Sector Erase Bulk Erase Deep Power-down Releasefrom Deep Power-down, and Read Electronic Signature Release from Deep Power-down

RES

Table 4. Status Register Format
b7 SRWD 0 0 BP2 BP1 BP0 WEL b0 WIP

Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit

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PART NUMBERING
Table 5. Ordering Information Scheme
Example: Device Type M25P = Serial Flash Memory for Code StorageDevice Function 32 = 32Mbit (4M x 8) 16 = 16Mbit (2M x 8) 80 = 8Mbit (1M x 8) 40 = 4Mbit (512K x 8) 20 = 2Mbit (256K x 8) 10-A = 1Mbit (128K x 8) 05-A = 512Kbit (64K x 8) Operating Voltage V = VCC = 2.7 to 3.6V Package ME = VDFPN8 8x6mm (MLP8) MP = VDFPN8 (MLP8) MF = SO16 (300 mil width) MN = SO8 (150 mil width) Device Grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard...